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參數(shù)資料
| 型號： | LT1680ISW#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 200 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.300 INCH, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 217K |
| 代理商： | LT1680ISW#TRPBF |
6
LT1680
RUN/SHDN Input Current
vs Pin Voltage
Operating Frequency
(Normalized) vs Temperature
Maximum Duty Cycle vs RCT
RCT (k)
12
4
6
MAXIMUM
DUTY
CYCLE
(%)
100
90
80
70
60
50
40
30
20
10
0
10
20
40 60 100
1680 G20
IDISCHG = 2.1mA
IDISCHG = 2.75mA
FULL OPERATING
TEMPERATURE
RANGE
TEMPERATURE (
°C)
–50
OPERATING
FREQUENCY
(NORMALIZED)
1.01
1.00
0.99
0.98
25
75
1680 G21
–25
0
50
100
125
RUN/SHDN PIN VOLTAGE (V)
0
RUN/SHDN
INPUT
CURRENT
(
A)
600
450
300
150
0
24
6
8
1680 G19
10
12
UPPER
LIMIT
LOWER
LIMIT
TYPICAL
FULL OPERATING
TEMPERATURE
RANGE
SL/ADJ (Pin 1): Slope Compensation Adjustment. Allows
increased slope compensation for certain high duty cycle
applications. Resistive loading of this pin increases effec-
tive slope compensation. A resistor divider from the 5VREF
pin can tailor the onset of additional slope compensation
to specific regions in each switch cycle. Pin can be floated
or connected to 5VREF if no additional slope compensation
is required. (See Applications Information section for
slope compensation details.)
CT (Pin 2): Oscillator Timing Pin. Connect a capacitor
(CCT) to ground and a pull-up resistor (RCT) to the 5VREF
supply. Typical values are CCT = 1000pF and 10k ≤ RCT ≤
30k.
IAVG (Pin 3): Average Current Limit Integration. The
frequency response characteristic is set using 50k
output impedance of this pin and external capacitor. The
external capacitor is typically connected from the IAVG pin
to the VC pin, but can also be connected from the IAVG pin
to ground. Connecting the capacitor from the IAVG pin to
the VC pin uses an internal gain block to form an active
integrator, minimizing the capacitance required for stable
operation. A typical value for this integration capacitor is
220pF from IAVG to VC. Shorting this pin to SGND will
disable the average current limit function.
SS (Pin 4): Soft Start. Generates ramping threshold for
regulator current limit during start-up and after UVLO
events by sourcing about 8
A into an external capacitor.
VC (Pin 5): Error Amplifier Output. RC load creates domi-
nant compensation in power supply regulation feedback
loop to provide optimum transient response. (See Appli-
cations Information section for compensation details.)
SGND (Pin 6): Small-Signal Ground. Connect to negative
terminal of COUT.
VFB (Pin 7): Error Amplifier Inverting Input. Used as
voltage feedback input node for regulator loop. Pin sources
about 0.5
A DC bias current to protect from an open
feedback path condition.
VREF (Pin 8): Bandgap Generated Voltage Reference
Decoupling. Connect a capacitor to signal ground. (Typi-
cal capacitor value
≈0.1F.)
SENSE + (Pin 9): Current Sense Amplifier Inverting Input.
Connect to most positive (DC) terminal of current sense
resistor.
SENSE – (Pin 10): Current Sense Amplifier Noninverting
Input. Connect to most negative (DC) terminal of current
sense resistor.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
UU
U
PI FU CTIO S
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