
LSM2 Series
Single Output, Non-isolated, Selectable-Output POL DC/DC Converters
MDC_LSM2_A01 Page 3 of 7
P O W E R E L E C T R O N I C S D I V I S I O N
D C / D C C O N V E R T E R S
www.cd4power.com
These diagrams illustrate the time and slew rate relationship between two
typical power output voltages. Generally the Master will be a primary power
voltage in the system which must be present first or coincident with any
Slave power voltages. The Master output voltage is connected to the Slave’s
Sequence input, either by a voltage divider, divider-plus-capacitor or some
other method. Several standard sequencing architectures are prevalent. They
are concerned with three factors:
n
The time relationship between the Master and Slave voltages
n
The voltage difference relationship between the Master and Slave
n
The voltage slew rate (ramp slope) of each converter’s output.
For most systems, the time relationship is the dominant factor. The voltage
difference relationship is important for systems very concerned about possible
latchup of programmable devices or overdriving ESD diodes. Lower slew
rates avoid overcurrent shutdown during bypass cap charge-up.
In Figure 0, two POL’s ramp up at the same rate until they reach their dif-
ferent respective final set point voltages. During the ramp, their voltages are
nearly identical. This avoids problems with large currents flowing between
Figures 2 and 3 show both delayed start up and delayed final voltages for
two converters. Figure 2 is called “Inclusive” because the later starting POL
finishes inside the earlier POL. The timing in Figure 2 is more easily built us-
ing a combined digital sequence controller and the Sequence/Track pin.
Figure 3 is the same strategy as Figure 2 but with an “exclusive” timing
relationship staggered approximately the same at power-up and power-down.
Operation
To use the Sequence pin after power start-up stabilizes, apply a rising external
voltage to the Sequence input. As the voltage rises, the output voltage will
track the Sequence input (gain = ). The output voltage will stop rising when
it reaches the normal set point for the converter. The Sequence input may op-
tionally continue to rise without any effect on the output. Keep the Sequence
input voltage below the converter’s input supply voltage.
Use a similar strategy on power down. The output voltage will stay constant
until the Sequence input falls below the set point.
Any strategy may be used to deliver the power up/down ramps. The circuits
below show simple RC networks but you may also use operational amplifiers,
D/A converters, etc.
Circuits
The circuits shown in Figures 4 through 6 introduce several concepts when
using these Sequencing controls on Point-of-Load (POL) converters. These
circuits are only for reference and are not intended as final designs ready for
your application. Also, numerous connections are omitted for clarity.
Figure 10. Coincident or Simultaneous Phasing (Identical Slew Rates)
Figure 11. Proportional or Ratiometric Phasing (Identical VOUT Time)
Figure 12. Staggered or Sequential Phasing—Inclusive (Fixed Delays)
Figure 13. Staggered or Sequential Phasing—Exclusive
(Fixed Cascaded Delays)
logic systems which are not initialized yet. Since both end voltages are differ-
ent, each converter reaches it’s setpoint voltage at a different time.
Figure shows two POL’s with different slew rates in order to reach differing
final voltages at about the same time.