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參數(shù)資料
| 型號(hào)： | LSIFC929 |
| 英文描述： | LSIFC929 dual channel fibre solutions |
| 中文描述： | LSIFC929雙通道光纖解決方案 |
| 文件頁(yè)數(shù)： | 47/144頁(yè) |
| 文件大?。?/td> | 1496K |
| 代理商： | LSIFC929 |
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4-7
Table 4.2
describes the FC 10-bit Interface signals.
Table 4.2
FC 10-Bit Interface Signals
Name
BGA Pos
Type Strength Description
TX[9:0]
N4, P3, P2, P1,
R3, R2, R1, T3,
T2, T1
O
8 mA
10-bit parallel data
to the PHY serializer device.
Data is clocked out to the PHY on the rising edge of
TBC. These pads contain an internal 100
μ
A pull-up.
RX[9:0]
C1, C2, D1, D2,
D3, E1, E2, E3,
E4, F1
I
N/A
10-bit parallel data
from the PHY serializer device.
Data is clocked into the LSIFC909 on the rising
edge of RBC[0] and RBC[1]. These pads contain an
internal 100
μ
A pull-up.
EN_CDET
U1
O
4 mA
Enable Comma Detect.
This pin enables the
comma detect circuitry on the PHY device to
establish byte synchronization on the next comma
that is received. This pad contains an internal
100
μ
A pull-up.
EWRAP
R4
O
4 mA
Electrically Wrap.
This pin causes the PHY device
to electrically wrap the serialized transmit data to the
deserializer and disables the laser output, if present.
This pad contains an internal 100
μ
A pull-up.
LCK_REF/ B3
O
4 mA
Lock Reference.
This pin causes the PHY device to
lock its receiver PLL to the TBC. This pad contains
an internal 100
μ
A pull-up.
TBC
N2
O
8 mA
Transmit Buffered Clock.
A buffered version of the
REFCLK input that is phase aligned to the TX data.
This pad contains an internal 100
μ
A pull-up.
RBC[1:0]
G3, F2
I
N/A
Receive Buffered Clock Inputs.
RBC[0] is the
clock from the PHY device used to latch RX into the
protocol device. RBC[1] is an optional clock that is
180 degrees out of phase from RBC[0]. This clock is
used to latch alternate bytes for 10-bit interface
compliant modules. These pads contain an internal
100
μ
A pull-up.
RXLOS
B1
I
N/A
Received Signal Loss.
Gigabit Interface Converter
(GBIC) has detected loss of signal.
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