4-5
FRAME/
AC6
S/T/S
16 mA
Cycle Frame
is driven by the current master to
indicate the beginning and duration of an access.
FRAME/ is asserted to indicate a bus transaction
is beginning. While FRAME/ is deasserted, the
transaction is in the final data phase or the bus is
idle.
IRDY/
AB6
S/T/S
16 mA
Initiator Ready
indicates the initiating agent’s
(bus master’s) ability to complete the current data
phase of the transaction. IRDY/ is used with
TRDY/. A data phase is completed on any clock
when both IRDY/ and TRDY/ are sampled
asserted. During a write, IRDY/ indicates that
valid data is present on AD[63:0]. During a read,
it indicates that the master is prepared to accept
data. Wait cycles are inserted until both IRDY/
and TRDY/ are asserted together.
TRDY/
AA6
S/T/S
16 mA
Target Ready
indicates the target agent’s
(selected device’s) ability to complete the current
data phase of the transaction. TRDY/ is used with
IRDY/. A data phase is completed on any clock
when used with IRDY/. A data phase is
completed on any clock when both TRDY/ and
IRDY/ are sampled asserted. During a read,
TRDY/ indicates that valid data is present on
AD[63:0]. During a write, it indicates that the
target is prepared to accept data. Wait cycles are
inserted until both IRDY/ and TRDY/ are asserted
together.
DEVSEL/
AC7
S/T/S
16 mA
Device Select
indicates that the driving device
has decoded its address as the target of the
current access. As an input, it indicates to a
master whether any device on the bus has been
selected.
STOP/
AA7
S/T/S
16 mA
Stop
indicates that the selected target is
requesting the master to stop the current
transaction.
Table 4.1
PCI Interface (Cont.) Signals
Name
BGA Pos
Type
Strength Description