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參數(shù)資料
| 型號(hào)： | LPC47M112 |
| 廠商： | SMSC Corporation |
| 英文描述： | ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE |
| 中文描述： | 增強(qiáng)的超級(jí)I / O控制器，LPC接口 |
| 文件頁(yè)數(shù)： | 84/228頁(yè) |
| 文件大?。?/td> | 1269K |
| 代理商： | LPC47M112 |
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SMSC DS – LPC47M192
Page 84
Rev. 03/30/05
DATASHEET
HOST
CONNECTOR
12
PIN NUMBER
78
STANDARD
PE
EPP
ECP
(User Defined)
PError,
nAckReverse (3)
Select
13
77
SLCT
(User Defined)
14
82
nALF
nDatastb
nAutoFd,
HostAck(3)
nFault (1)
nPeriphRequest (3)
nInit(1)
nReverseRqst(3)
nSelectIn(1,3)
15
81
nERROR
(User Defined)
16
66
nINIT
nRESET
17
67
nSLCTIN
nAddrstrb
(1) = Compatible Mode
(3) = High Speed Mode
Note
:
For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document is
available from Microsoft.
7.8.1 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES
DATA PORT
ADDRESS OFFSET = 00H
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of
this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP
mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU.
STATUS PORT
ADDRESS OFFSET = 01H
The Status Port is located at an offset of ‘01H’ from the base address. The contents of this register are latched for
the duration of a read cycle. The bits of the Status Port are defined as follows:
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O
means that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is
cleared by a RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device
3 Configuration Registers) is ‘0’, writing a one to this bit clears the TMOUT status bit. Writing a zero to this bit has no
effect. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3
Configuration Registers) is ‘1’, the TMOUT bit is cleared on the trailing edge of a read of the EPP Status Register.
BITS 1, 2
-
are not implemented as register bits, during a read of the Printer Status Register these bits are a low
level.
BIT 3 nERR – nERROR
The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error
has been detected; a logic 1 means no error has been detected.
BIT 4 SLT - PRINTER SELECTED STATUS
The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is
on line; a logic 0 means it is not selected.
BIT 5 PE - PAPER END
The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end;
a logic 0 indicates the presence of paper.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LPC47M112-MC | ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE |
| LPC47M112-MW | ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE |
| LPC47N252-SD | Advanced Notebook I/O Controller with On-Board FLASH |
| LPC47N252-SG | Advanced Notebook I/O Controller with On-Board FLASH |
| LPC47M172-NR | ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC47M112_07 | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:Enhanced Super I/O Controller with LPC Interface |
| LPC47M112-MC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| LPC47M112-MW | 功能描述:以太網(wǎng) IC Enhanced Super I/O Cntrl LPC Interface RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LPC47M133-NC | 制造商:SMSC 功能描述: |
| LPC47M140-NC | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
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