參數(shù)資料
型號(hào)： LPC2939FBD208
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： ARM9 microcontroller with CAN, LIN, and USB
中文描述： 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP208
封裝： 28 X 28 MM, 1.40 MM HEIGHT, PLASTIC, SOT-459, MS-026, LQFP-208
文件頁(yè)數(shù)： 56/99頁(yè)
文件大小： 1945K
代理商： LPC2939FBD208
LPC2939_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2010
56 of 99
NXP Semiconductors
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
Triple output phases:
For applications that require multiple clock phases two additional
clock outputs can be enabled by setting register P23EN to logic 1, thus giving three clocks
with a 120
phase difference. In this mode all three clocks generated by the analog
section are sent to the output dividers. When the PLL has not yet achieved lock the
second and third phase output dividers run unsynchronized, which means that the phase
relation of the output clocks is unknown. When the PLL LOCK register is set the second
and third phase of the output dividers are synchronized to the main output clock CLKOUT
PLL, thus giving three clocks with a 120
phase difference.
Direct output mode:
In normal operating mode (with DIRECT set to logic 0) the CCO
clock is divided by 2, 4, 8 or 16 depending on the value on the PSEL[1:0] input, giving an
output clock with a 50 % duty cycle. If a higher output frequency is needed the CCO clock
can be sent directly to the output by setting DIRECT to logic 1. Since the CCO does not
directly generate a 50 % duty cycle clock, the output clock duty cycle in this mode can
deviate from 50 %.
Power-down control:
A Power-down mode has been incorporated to reduce power
consumption when the PLL clock is not needed. This is enabled by setting the PD control
register bit. In this mode the analog section of the PLL is turned off, the oscillator and the
phase-frequency detector are stopped and the dividers enter a reset state. While in
Power-down mode the LOCK output is LOW, indicating that the PLL is not in lock. When
Power-down mode is terminated by clearing the PD control-register bit the PLL resumes
normal operation, and makes the LOCK signal HIGH once it has regained lock on the
input clock.
6.16.2.3
Pin description
The CGU0 module in the LPC2939 has the pins listed in
Table 28
below.
Table 28.
Symbol
XOUT_OSC
XIN_OSC
Fig 14. PLL block diagram
CCO
/ 2PDIV
P23
/ MDIV
002aad833
bypass
direct
clkout120
clkout240
clkout
clkout
input clock
PSEL bits
P23EN bit
MSEL bits
CGU0 pins
Direction
OUT
IN
Description
Oscillator crystal output
Oscillator crystal input or external clock input
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