參數(shù)資料
型號(hào)： LPC2939FBD208
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： ARM9 microcontroller with CAN, LIN, and USB
中文描述： 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP208
封裝： 28 X 28 MM, 1.40 MM HEIGHT, PLASTIC, SOT-459, MS-026, LQFP-208
文件頁(yè)數(shù)： 47/99頁(yè)
文件大?。?/td> 1945K
代理商： LPC2939FBD208
LPC2939_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 7 April 2010
47 of 99
NXP Semiconductors
LPC2939
ARM9 microcontroller with CAN, LIN, and USB
The PWM block diagram in
Figure 10
shows the basic architecture of each PWM. PWM
functionality is split into two major parts, a APB domain and a PWM domain, both of which
run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects
behavior from a system-level perspective. The actual PWM and prescale counters are
located in the PWM domain but system control takes place in the APB domain.
The actual PWM consists of two counters; a 16-bit prescale counter and a 16-bit PWM
counter. The position of the rising and falling edges of the PWM outputs can be
programmed individually. The prescale counter allows high system bus frequencies to be
scaled down to lower PWM periods. Registers are available to capture the PWM counter
values on external events.
Note that in the Modulation and Sampling SubSystem, each PWM has its individual clock
source CLK_MSCSS_PWMx (x runs from 0 to 3). Both the prescale and the timer
counters within each PWM run on this clock CLK_MSCSS_PWMx, and all time references
are related to the period of this clock. See
Section 6.16
for information on generation of
these clocks.
6.15.5.2
Synchronizing the PWM counters
A mechanism is included to synchronize the PWM period to other PWMs by providing a
sync input and a sync output with programmable delay. Several PWMs can be
synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports.
See
Figure 8
for details of the connections of the PWM modules within the MSCSS in the
LPC2939. PWM 0 can be master over PWM 1; PWM 1 can be master over PWM 2, etc.
Fig 10. PWM block diagram
002aad837
APB system bus
IRQ pwm
IRQ capt_match
PWM
CONTROL
&
REGISTERS
update
capture data
PWM counter value
config data
IRQs
PWM,
COUNTER,
PRESCALE
COUNTER
&
SHADOW
REGISTERS
match outputs
capture inputs
trap input
carrier inputs
sync_in
sync_out
transfer_enable_in
transfer_enable_out
APB DOMAIN
PWM DOMAIN
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