參數(shù)資料
型號(hào)： LPC2929FBD144
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： ARM9 microcontroller with CAN, LIN, and USB
中文描述： 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁(yè)數(shù)： 33/95頁(yè)
文件大小： 1855K
代理商： LPC2929FBD144
LPC2926_27_29
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 28 September 2010
33 of 95
NXP Semiconductors
LPC2926/2927/2929
ARM9 microcontroller with CAN, LIN, and USB
6.13.4
UARTs
The LPC2926/2927/2929 contains two identical UARTs located at different peripheral
base addresses. The key features are:
16-byte receive and transmit FIFOs.
Register locations conform to 550 industry standard.
Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes.
Built-in baud rate generator.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UART is commonly used to implement a serial interface such as RS232. The
LPC2926/2927/2929 contains two industry-standard 550 UARTs with 16-byte transmit and
receive FIFOs, but they can also be put into 450 mode without FIFOs.
Remark:
The LIN controller can be configured to provide two additional standard UART
interfaces (see
Section 6.14.2
).
6.13.4.1
Pin description
The UART pins are combined with other functions on the port pins of the
LPC2926/2927/2929.
Table 17
shows the UART pins (x runs from 0 to 1).
Table 17.
Symbol
UARTx TXD
UARTx RXD
6.13.4.2
Clock description
The UART modules are clocked by two different clocks; CLK_SYS_PESS and
CLK_UARTx (x = 0 to 1), see
Section 6.7.2
. Note that each UART has its own
CLK_UARTx branch clock for power management. The frequency of all CLK_UARTx
clocks is identical since they are derived from the same base clock BASE_CLK_UART.
The register interface towards the system bus is clocked by CLK_SYS_PESS. The baud
generator is clocked by the CLK_UARTx.
6.13.5
Serial Peripheral Interface (SPI)
The LPC2926/2927/2929 contains three Serial Peripheral Interface modules (SPIs) to
allow synchronous serial communication with slave or master peripherals.
The key features are:
Master or slave operation.
Each SPI supports up to four slaves in sequential multi-slave operation.
Supports timer-triggered operation.
Programmable clock bit rate and prescale based on SPI source clock
(BASE_SPI_CLK), independent of system clock.
Separate transmit and receive FIFO memory buffers; 16 bits wide, 32 locations deep.
UART pins
Pin name
TXDx
RXDx
Direction
OUT
IN
Description
UART channel x transmit data output
UART channel x receive data input
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