參數(shù)資料
型號: LPC2929FBD144
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT486-1, LQFP-144
文件頁數(shù): 18/95頁
文件大?。?/td> 1855K
代理商: LPC2929FBD144
LPC2926_27_29
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 28 September 2010
18 of 95
NXP Semiconductors
LPC2926/2927/2929
ARM9 microcontroller with CAN, LIN, and USB
6.7.2
Base clock and branch clock relationship
Table 7
contains an overview of all the base blocks in the LPC2926/2927/2929 and their
derived branch clocks. A short description is given of the hardware parts that are clocked
with the individual branch clocks. In relevant cases more detailed information can be
found in the specific subsystem description. Some branch clocks have special protection
since they clock vital system parts of the device and should not be switched off. See
Section 6.16.5
for more details of how to control the individual branch clocks.
Table 7.
Base clock
CGU0 base clock and branch clock overview
Branch clock name
Parts of the device clocked
by this branch clock
watchdog timer
ARM968E-S and TCMs
AHB bus infrastructure
AHB side of bridge in PCRSS
Flash Memory Controller
Embedded SRAM Controller 0
(32 kB)
Embedded SRAM Controller 1
(16 kB)
External Static Memory
Controller
General Subsystem
Vectored Interrupt Controller
Peripheral Subsystem
GPIO bank 0
GPIO bank 1
GPIO bank 2
GPIO bank 3
GPIO bank 5
AHB side of bridge of IVNSS
AHB side of bridge of MSCSS
GPDMA
USB registers
PCRSS, CGU, RGU and PMU
logic clock
APB side of the IVNSS
CAN controller Acceptance
Filter
CAN channel 0
CAN channel 1
I2C0
I2C1
LIN channel 0
LIN channel 1
Remark
BASE_SAFE_CLK
BASE_SYS_CLK
CLK_SAFE
CLK_SYS_CPU
CLK_SYS_SYS
CLK_SYS_PCRSS
CLK_SYS_FMC
CLK_SYS_RAM0
[1]
CLK_SYS_RAM1
CLK_SYS_SMC
CLK_SYS_GESS
CLK_SYS_VIC
CLK_SYS_PESS
CLK_SYS_GPIO0
CLK_SYS_GPIO1
CLK_SYS_GPIO2
CLK_SYS_GPIO3
CLK_SYS_GPIO5
CLK_SYS_IVNSS_A
CLK_SYS_MSCSS_A
CLK_SYS_DMA
CLK_SYS_USB
CLK_PCR_SLOW
[2][3]
BASE_PCR_CLK
[1][4]
BASE_IVNSS_CLK
CLK_IVNSS_APB
CLK_IVNSS_CANCA
CLK_IVNSS_CANC0
CLK_IVNSS_CANC1
CLK_IVNSS_I2C0
CLK_IVNSS_I2C1
CLK_IVNSS_LIN0
CLK_IVNSS_LIN1
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