參數(shù)資料
型號(hào): LPC2478FET208
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: Single-chip 16-bit-32-bit micro; 512 kB flash, Ethernet, CAN, LCD, USB 2.0 device-host-OTG, external memory interface
封裝: LPC2478FBD208<SOT459-1 (LQFP208)|<<http://www.nxp.com/packages/SOT459-1.html<1<Always Pb-free,;LPC2478FET208<SOT950-1 (TFBGA208)|<<http://www.nxp.com/packages/SOT950-1.ht
文件頁(yè)數(shù): 5/93頁(yè)
文件大?。?/td> 751K
代理商: LPC2478FET208
LPC2478
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 12 September 2011
5 of 93
NXP Semiconductors
LPC2478
Single-chip 16-bit/32-bit microcontroller
5. Block diagram
Fig 1.
LPC2478 block diagram
power domain 2
LPC2478
A[23:0]
control lines
D[31:0]
EXTERNAL
MEMORY
CONTROLLER
ALARM
002aac805
PWM0, PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
64 PINS TOTAL
P0, P1
SCK0, SCK
MOSI0, MOSI
MISO0, MISO
3
×
I2STX
3
×
I2SRX
8
×
LCD control
LCDVD[23:0]
LCDCLKIN
SSEL0, SSEL
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
8
×
AD0
RTCX1
RTCX2
MCICLK, MCIPWR
MCICMD,
MCIDAT[3:0]
RXD0, RXD2, RXD3
RD1, RD2
TD1, TD2
CAN1, CAN2
port1
port2
XTAL1
TCK TDO
EXTIN0
XTAL2
RESET
TRST
TDI
TMS
HIGH-SPEED
GPIO
160 PINS
TOTAL
64 kB
SRAM
512 kB
FLASH
INTERNAL
CONTROLLERS
SRAM
TEST/DEBUG
INTERFACE
E
T
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
V
DD(DCDC)(3V3)
VREF
V
SSA
, V
SSIO,
V
SSCORE
VIC
16 kB
SRAM
USB DEVICE/
HOST/OTG WITH
4 kB RAM AND DMA
GP DMA
CONTROLLER
LCD INTERFACE
WITH DMA
I
2
S INTERFACE
SSP0/SPI INTERFACE
SSP1 INTERFACE
SD/MMC CARD
INTERFACE
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
TXD1, DTR1, RTS1
RXD1, DSR1, CTS1,
DCD1, RI1
I
2
C0, I
2
C1, I
2
C2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2
×
CAP0/CAP1/
CAP2/CAP3
4
×
MAT2/MAT3,
2
×
MAT0,
3
×
MAT1
6
×
PWM0/PWM1
1
×
PCAP0,
2
×
PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
MII/RMII
V
BUS
DBGEN
P0, P2
AHB2
AHB1
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