參數(shù)資料
型號: LPC2460FET208
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: Flashless 16-bit-32-bit microcontroller; Ethernet, CAN, ISP-IAP, USB 2.0 device-host-OTG, external memory interface
封裝: LPC2420FBD208<SOT459-1 (LQFP208)|<<http://www.nxp.com/packages/SOT459-1.html<1<Always Pb-free,;LPC2420FET208<SOT950-1 (TFBGA208)|<<http://www.nxp.com/packages/SOT950-1.ht
文件頁數(shù): 7/86頁
文件大?。?/td> 496K
代理商: LPC2460FET208
LPC2420_60
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6.1 — 22 September 2011
7 of 86
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
17
P1[5]/ENET_TX_ER/
MCIPWR/PWM0[3]
Row B
1
P3[2]/D2
5
P1[1]/ENET_TXD1
9
P4[25]/WE
-
-
-
2
6
10
P3[10]/D10
V
SSIO
P4[29]/BLS3/
MAT2[1]/RXD3
P3[19]/D19/
PWM0[4]/DCD1
-
3
7
11
P3[1]/D1
P4[30]/CS0
P1[6]/ENET_TX_CLK/
MCIDAT0/PWM0[4]
P4[14]/A14
4
8
12
P3[0]/D0
P4[24]/OE
P0[4]/I2SRX_CLK/RD2/
CAP2[0]
P4[13]/A13
13
V
DD(3V3)
14
15
16
17
P2[0]/PWM1[1]/TXD1/
TRACECLK
Row C
1
P3[13]/D13
5
P3[9]/D9
-
-
2
6
TDI
P3[22]/D22/
PCAP0[0]/RI1
P3[21]/D21/
PWM0[6]/DTR1
P0[9]/I2STX_SDA/
MOSI1/MAT2[3]
-
3
7
RTCK
P1[8]/ENET_CRS_DV/
ENET_CRS
P4[28]/BLS2/
MAT2[0]/TXD3
P3[18]/D18/
PWM0[3]/CTS1
-
4
8
P0[2]/TXD0
P1[10]/ENET_RXD1
9
V
DD(3V3)
10
11
12
P0[5]/I2SRX_WS/TD2/
CAP2[1]
P4[12]/A12
13
P0[7]/I2STX_CLK/SCK1
/MAT2[1]
V
DD(3V3)
Row D
1
TRST
14
15
16
17
-
2
P3[28]/D28/
CAP1[1]/PWM1[5]
P0[3]/RXD0
P1[16]/ENET_MDC
3
TDO
4
P3[12]/D12
5
9
P3[11]/D11
P1[2]/ENET_TXD2/
MCICLK/PWM0[1]
P0[6]/I2SRX_SDA/
SSEL1/MAT2[0]
P2[4]/PWM1[5]/
DSR1/TRACESYNC
Row E
1
P0[26]/AD0[3]/
AOUT/RXD3
14
P2[1]/PWM1[2]/RXD1/
PIPESTAT0
Row F
1
P0[25]/AD0[2]/
I2SRX_SDA/TXD3
14
P4[11]/A11
6
10
7
11
V
DD(3V3)
V
DD(DCDC)(3V3)
8
12
P3[8]/D8
V
SSCORE
13
14
P1[7]/ENET_COL/
MCIDAT1/PWM0[5]
-
15
P2[2]/PWM1[3]/
CTS1/PIPESTAT1
-
16
P1[13]/ENET_RX_DV
17
-
2
TCK
3
TMS
4
P3[3]/D3
15
V
SSIO
16
P2[3]/PWM1[4]/
DCD1/PIPESTAT2
17
P2[6]/PCAP1[0]/
RI1/TRACEPKT1
2
P3[4]/D4
3
P3[29]/D29/
MAT1[0]/PWM1[6]
P2[5]/PWM1[6]/
DTR1/TRACEPKT0
4
DBGEN
15
P3[17]/D17/
PWM0[2]/RXD1
16
17
P3[16]/D16/
PWM0[1]/TXD1
Row G
1
P3[5]/D5
2
P0[24]/AD0[1]/
I2SRX_WS/CAP3[1]
P4[27]/BLS1
3
V
DD(3V3)
4
V
DDA
14
n.c.
15
16
P2[7]/RD2/
RTS1/TRACEPKT2
17
P4[10]/A10
Table 3.
Pin Symbol
Pin allocation table
…continued
Pin Symbol
Pin Symbol
Pin Symbol
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