參數(shù)資料
型號(hào)： LPC2460FET208
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： Flashless 16-bit-32-bit microcontroller; Ethernet, CAN, ISP-IAP, USB 2.0 device-host-OTG, external memory interface
封裝： LPC2420FBD208<SOT459-1 (LQFP208)|<<http://www.nxp.com/packages/SOT459-1.html<1<Always Pb-free,;LPC2420FET208<SOT950-1 (TFBGA208)|<<http://www.nxp.com/packages/SOT950-1.ht
文件頁(yè)數(shù)： 62/86頁(yè)
文件大?。?/td> 496K
代理商： LPC2460FET208
LPC2420_60
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6.1 — 22 September 2011
62 of 86
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
[1]
See
Figure 18
.
Table 16.
C
L
= 30 pF, T
amb
=
40
C to 85
C, V
DD(DCDC)(3V3)
= V
DD(3V3)
= 3.3 V, EMC Dynamic Read Config Register = 0x1 (RD = 01),
T
cy(CCLK)
= 1/CCLK
Symbol
Parameter
Conditions
Common
t
d(SV)
chip select valid delay
time
t
h(S)
chip select hold time
t
d(RASV)
row address strobe valid
delay time
t
h(RAS)
row address strobe hold
time
t
d(CASV)
column address strobe
valid delay time
t
h(CAS)
column address strobe
hold time
t
d(WV)
write valid delay time
t
h(W)
write hold time
t
d(GV)
output enable valid delay
time
t
h(G)
output enable hold time
t
d(AV)
address valid delay time
t
h(A)
address hold time
Read cycle parameters
t
su(D)
data input set-up time
t
h(D)
data input hold time
Write cycle parameters
t
d(QV)
data output valid delay
time
t
h(Q)
data output hold time
Dynamic characteristics: Dynamic external memory interface
Min
Typ
Max
Unit
[1]
-
3 + T
cy(CCLK)
1.5 + T
cy(CCLK)
ns
[1]
4 + T
cy(CCLK)
[1]
-
3 + T
cy(CCLK)
3 + T
cy(CCLK)
-
1.5 + T
cy(CCLK)
ns
ns
[1]
3 + T
cy(CCLK)
2.3 + T
cy(CCLK)
-
ns
[1]
-
3.4 + T
cy(CCLK)
2.1 + T
cy(CCLK)
ns
[1]
4 + T
cy(CCLK)
3 + T
cy(CCLK)
-
ns
[1]
-
3.4 + T
cy(CCLK)
2.1 + T
cy(CCLK)
3 + T
cy(CCLK)
3 + T
cy(CCLK)
ns
ns
ns
[1]
4 + T
cy(CCLK)
[1]
-
-
1.3 + T
cy(CCLK)
[1]
4 + T
cy(CCLK)
[1]
-
2.1 + T
cy(CCLK)
-
2.6 + T
cy(CCLK)
1.4 + T
cy(CCLK)
2.3 + T
cy(CCLK)
-
ns
ns
[1]
4 + T
cy(CCLK)
ns
[1]
2.6 + T
cy(CCLK)
1.5 + T
cy(CCLK)
-
[1]
2.6 + T
cy(CCLK)
1.3 + T
cy(CCLK)
-
ns
ns
[1]
-
2.6 + T
cy(CCLK)
3 + T
cy(CCLK)
ns
[1]
3.8 + T
cy(CCLK)
3.4 + T
cy(CCLK)
-
ns
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