參數(shù)資料
型號： LPC2460FET208
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： Flashless 16-bit-32-bit microcontroller; Ethernet, CAN, ISP-IAP, USB 2.0 device-host-OTG, external memory interface
封裝： LPC2420FBD208<SOT459-1 (LQFP208)|<<http://www.nxp.com/packages/SOT459-1.html<1<Always Pb-free,;LPC2420FET208<SOT950-1 (TFBGA208)|<<http://www.nxp.com/packages/SOT950-1.ht
文件頁數(shù)： 43/86頁
文件大?。?/td> 496K
代理商： LPC2460FET208
LPC2420_60
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6.1 — 22 September 2011
43 of 86
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
7.24.4
Power control
The LPC2420/2460 supports a variety of power control features. There are four special
modes of processor power reduction: Idle mode, Sleep mode, Power-down mode, and
Deep power-down mode. The CPU clock rate may also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This allows a trade-off of power versus processing speed based on application
requirements. In addition, Peripheral power control allows shutting down the clocks to
individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all
dynamic power use in any peripherals that are not required for the application. Each of the
peripherals has its own clock divider which provides even better power control.
The LPC2420/2460 also implements a separate power domain in order to allow turning off
power to the bulk of the device while maintaining operation of the RTC and a small SRAM,
referred to as the Battery RAM.
7.24.4.1
Idle mode
In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.24.4.2
Sleep mode
In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The
processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Sleep mode and the logic levels of chip pins remain static. The
output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The
32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the
wake-up source. The PLL is automatically turned off and disconnected. The CCLK and
USB clock dividers automatically get reset to zero.
The Sleep mode can be terminated and normal operation resumed by either a Reset or
certain specific interrupts that are able to function without clocks. Since all dynamic
operation of the chip is suspended, Sleep mode reduces chip power consumption to a
very low value.
On the wake-up from Sleep mode, if the IRC was used before entering Sleep mode, the
code execution and peripherals activities will resume after 4 cycles expire. If the main
external oscillator was used, the code execution will resume when 4096 cycles expire.
The customers need to reconfigure the PLL and clock dividers accordingly.
7.24.4.3
Power-down mode
Power-down mode does everything that Sleep mode does but also turns off the IRC
oscillator.
On the wake-up from Power-down mode, if the IRC was used before entering
Power-down mode, it will take IRC 60
s to start-up. After this 4 IRC cycles will expire
before the code execution can then be resumed if the code was running from SRAM. The
customers need to reconfigure the PLL and clock dividers accordingly after a wake-up
from Power-down mode.
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