參數(shù)資料
型號(hào)： LPC2388
廠商： NXP Semiconductors N.V.
英文描述： Single-chip 16-bit/32-bit microcontroller; 512 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC
中文描述： 單芯片16-bit/32-bit微控制器，512的ISP /國(guó)際檢察官聯(lián)合會(huì)，以太網(wǎng)，USB 2.0設(shè)備kB閃存/主機(jī)/ OTG公司，CAN和10位的ADC / DAC
文件頁(yè)數(shù)： 23/57頁(yè)
文件大小： 325K
代理商： LPC2388
LPC2388_0
NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 00.02 — 28 January 2008
23 of 57
NXP Semiconductors
LPC2388
Fast communication chip
7.11 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The Host Controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
Host Controller.
The LPC2388 USB interface includes a device, Host, and OTG Controller. Details on
typical USB interfacing solutions can be found in
Section 11.1
.
7.11.1
USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host Controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the USB
RAM.
7.11.1.1
Features
Fully compliant with USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While the USB is in the Suspend mode, the LPC2388 can enter one of the reduced
power modes and wake up on USB activity.
Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints.
Allows dynamic switching between CPU-controlled and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
7.11.2
USB Host Controller
The Host Controller enables full- and low-speed data exchange with USB devices
attached to the bus. It consists of register interface, serial interface engine and DMA
controller. The register interface complies with the OHCI specification.
7.11.2.1
Features
OHCI compliant.
Two downstream ports.
Supports per-port power switching.
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