參數(shù)資料
型號: LPC2364FBD100
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: ARM7 with 128 kB flash, 34 kB SRAM, Ethernet, USB 2.0 Device, CAN, and 10-bit ADC
封裝: LPC2364FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁數(shù): 17/69頁
文件大?。?/td> 517K
代理商: LPC2364FBD100
LPC2364_65_66_67_68
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 20 October 2011
17 of 69
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
[1]
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[2]
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input,
digital section of the pad is disabled.
[3]
5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
[4]
Open-drain 5 V tolerant digital I/O pad, compatible with I
2
C-bus 400 kHz specification. This pad requires an external pull-up to provide
output functionality. When power is switched off, this pin connected to the I
2
C-bus is floating and does not disturb the I
2
C lines.
Open-drain configuration applies to all functions on this pin.
[5]
Pad provides digital I/O and USB functions (LPC2364/66/68 only). It is designed in accordance with the
USB specification, revision 2.0
(Full-speed and Low-speed mode only).
[6]
5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
[7]
This pin has no built-in pull-up and no built-in pull-down resistor.
[8]
This pin has a built-in pull-up resistor.
[9]
5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[10] Pad provides special analog functionality.
[11] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
RSTOUT
14
-
O
RSTOUT —
This is a 3.3 V pin. LOW on this pin indicates
LPC2364/65/66/67/68 being in Reset state.
Note:
This pin is available in LPC2364FBD100, LPC2365FBD100,
LPC2366FBD100, LPC2367FBD100, and LPC2368FBD100 devices only
(LQFP100 package).
External reset input:
A LOW on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
ground:
0 V reference.
RESET
17
[9]
F3
[9]
I
XTAL1
XTAL2
RTCX1
RTCX2
V
SS
22
[10][11]
23
[10][11]
16
[10][12]
18
[10]
15, 31,
41, 55,
72, 97,
83
[13]
11
[14]
H2
[10][11]
I
G3
[10][11]
O
F2
[10][12]
G1
[10]
B3, B7,
C9, F1,
G7, J6,
K3
[13]
E1
[14]
I
O
I
V
SSA
I
analog ground:
0 V reference. This should nominally be the same voltage
as V
SS
, but should be isolated to minimize noise and error.
3.3 V supply voltage:
This is the power supply voltage for the I/O ports.
V
DD(3V3)
28, 54,
71,
96
[15]
A3, C10,
H9,
K2
[15]
I
V
DD(DCDC)(3V3)
13, 42,
84
[16]
10
[17]
A7, E4,
H6
[16]
E2
[17]
I
3.3 V DC-to-DC converter supply voltage:
This is the supply voltage for
the on-chip DC-to-DC converter only.
analog 3.3 V pad supply voltage:
This should be nominally the same
voltage as V
DD(3V3)
but should be isolated to minimize noise and error. This
voltage is used to power the ADC and DAC.
ADC reference:
This should be nominally the same voltage as V
DD(3V3)
but
should be isolated to minimize noise and error. Level on this pin is used as
a reference for ADC and DAC.
RTC pin power supply:
3.3 V on this pin supplies the power to the RTC
peripheral.
V
DDA
I
VREF
12
[17]
E3
[17]
I
VBAT
19
[17]
G2
[17]
I
Table 4.
Symbol
Pin description
…continued
Pin
Ball
Type
Description
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