參數(shù)資料
型號(hào): LPC2361FBD100
廠商: NXP Semiconductors N.V.
元件分類(lèi): 數(shù)學(xué)處理器
英文描述: Single-chip 16-bit-32-bit MCU; up to 128 kB flash with ISP-IAP, Ethernet, USB 2.0 device-host-OTG, CAN, and 10-bit ADC-DAC
封裝: LPC2361FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;LPC2362FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.htm
文件頁(yè)數(shù): 4/64頁(yè)
文件大?。?/td> 475K
代理商: LPC2361FBD100
LPC2361_62
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 25 October 2011
4 of 64
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
5. Block diagram
(1) LPC2362 only.
Fig 1.
LPC2361/2362 block diagram
PWM1
ARM7TDMI-S
PLL
EINT3 to EINT0
FLASH
P3, P4
P0, P1, P2,
LEGACY GPI/O
52 PINS TOTAL
P0, P1
SCK, SCK0
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
I2SRX_SDA
I2STX_SDA
6
×
AD0
RTCX1
RTCX2
RXD0, RXD2, RXD3
TXD1
RXD1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
RD1, RD2
TD1, TD2
CAN1, CAN2
USB port 1
XTAL1
TCK TDO
EXTIN0
XTAL2
RESET
TRST
TDI
TMS
HIGH-SPEED
GPI/O
70 PINS
TOTAL
LPC2361/62
8/32 kB
SRAM
64/128 kB
FLASH
INTERNAL
CONTROLLERS
SRAM
TEST/DEBUG
INTERFACE
E
T
trace signals
AHB
BRIDGE
AHB
BRIDGE
ETHERNET
MAC WITH
DMA
(1)
16 kB
SRAM
MASTER
PORT
AHB TO
AHB BRIDGE
SLAVE
PORT
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
V
DDA
V
DD(3V3)
VREF
V
SSA
, V
SS
V
DD(DCDC)(3V3)
VECTORED
INTERRUPT
CONTROLLER
8 kB
SRAM
USB WITH
4 kB RAM
AND DMA
GP DMA
CONTROLLER
I
2
S INTERFACE
SPI, SSP0 INTERFACE
SSP1 INTERFACE
TXD0, TXD2, TXD3
UART0, UART2, UART3
UART1
I
2
C0, I
2
C1, I
2
C2
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
A/D CONVERTER
D/A CONVERTER
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
2
×
CAP0/CAP1/
CAP2/CAP3
4
×
MAT2,
2
×
MAT0/MAT1/
MAT3
6
×
PWM1
2
×
PCAP1
AOUT
VBAT
AHB TO
APB BRIDGE
RMII(8)
V
BUS
002aad964
P0, P2
power domain 2
AHB2
AHB1
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