參數(shù)資料
型號(hào)： LPC2361FBD100
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： Single-chip 16-bit-32-bit MCU; up to 128 kB flash with ISP-IAP, Ethernet, USB 2.0 device-host-OTG, CAN, and 10-bit ADC-DAC
封裝： LPC2361FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;LPC2362FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.htm
文件頁數(shù)： 12/64頁
文件大?。?/td> 475K
代理商： LPC2361FBD100
LPC2361_62
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 25 October 2011
12 of 64
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
[1]
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[2]
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input,
digital section of the pad is disabled.
P4[28]/MAT2[0]/
TXD3
82
[1]
I/O
O
O
I/O
O
I
O
I
I
I
I
P4[28] —
General purpose digital input/output pin.
MAT2[0] —
Match output for Timer 2, channel 0.
TXD3 —
Transmitter output for UART3.
P4[29] —
General purpose digital input/output pin.
MAT2[1] —
Match output for Timer 2, channel 1.
RXD3 —
Receiver input for UART3.
TDO —
Test Data out for JTAG interface.
TDI —
Test Data in for JTAG interface.
TMS —
Test Mode Select for JTAG interface.
TRST —
Test Reset for JTAG interface.
TCK —
Test Clock for JTAG interface. This clock must be slower than
1
6
of the
CPU clock (CCLK) for the JTAG interface to operate
RTCK —
JTAG interface control signal.
Note:
LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to
operate as trace port after reset.
RSTOUT —
This is a 3.3 V pin. LOW on this pin indicates LPC2361/2362 being in
Reset state.
External reset input:
A LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
P4[29]/MAT2[1]/
RXD3
85
[1]
TDO
TDI
TMS
TRST
TCK
1
[1][7]
2
[1][8]
3
[1][8]
4
[1][8]
5
[1][7]
RTCK
100
[1][8]
I/O
RSTOUT
14
O
RESET
17
[9]
I
XTAL1
XTAL2
RTCX1
RTCX2
V
SS
22
[10][11]
23
[10][11]
16
[10][12]
18
[10][12]
15, 31,
41, 55,
72, 97,
83
[13]
11
[14]
I
O
I
O
I
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
ground:
0 V reference.
V
SSA
I
analog ground:
0 V reference. This should nominally be the same voltage as
V
SS
, but should be isolated to minimize noise and error.
3.3 V supply voltage:
This is the power supply voltage for the I/O ports.
V
DD(3V3)
28, 54,
71,
96
[15]
13, 42,
84
[16]
10
[17]
I
V
DD(DCDC)(3V3)
I
3.3 V DC-to-DC converter supply voltage:
This is the supply voltage for the
on-chip DC-to-DC converter only.
analog 3.3 V pad supply voltage:
This should be nominally the same voltage as
V
DD(3V3)
but should be isolated to minimize noise and error. This voltage is used to
power the ADC and DAC.
ADC reference:
This should be nominally the same voltage as V
DD(3V3)
but
should be isolated to minimize noise and error. Level on this pin is used as a
reference for ADC and DAC.
RTC power supply:
3.3 V on this pin supplies the power to the RTC peripheral.
V
DDA
I
VREF
12
[17]
I
VBAT
19
[17]
I
Table 3.
Symbol
Pin description
…continued
Pin
Type
Description
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