參數(shù)資料
型號: LPC2290FBD144
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 16-32-bit ARM microcontroller with CAN, 10-bit ADC and external memory interface
封裝: LPC2290FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;
文件頁數(shù): 12/41頁
文件大小: 198K
代理商: LPC2290FBD144
LPC2290_3
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 16 November 2006
12 of 41
NXP Semiconductors
LPC2290
16/32-bit ARM microcontroller with external memory interface
P3.20/A20
45
[5]
I/O
O
I/O
O
I/O
O
I/O
I/O
O
I/O
O
P3.20 —
General purpose digital input/output pin.
A20 —
External memory address line 20.
P3.21 —
General purpose digital input/output pin.
A21 —
External memory address line 21.
P3.22 —
General purpose digital input/output pin.
A22 —
External memory address line 22.
P3.23 —
General purpose digital input/output pin.
A23 —
External memory address line 23.
XCLK —
Clock output.
P3.24 —
General purpose digital input/output pin.
CS3 —
LOW-active Chip Select 3 signal.
(Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF)
P3.25 —
General purpose digital input/output pin.
CS2 —
LOW-active Chip Select 2 signal.
(Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF)
P3.26 —
General purpose digital input/output pin.
CS1 —
LOW-active Chip Select 1 signal.
(Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF)
P3.27 —
General purpose digital input/output pin.
WE —
LOW-active Write enable signal.
P3.28 —
General purpose digital input/output pin.
BLS3 —
LOW-active Byte Lane Select signal (Bank 3).
AIN7 —
ADC, input 7. This analog input is always connected to its pin.
P3.29 —
General purpose digital input/output pin.
BLS2 —
LOW-active Byte Lane Select signal (Bank 2).
AIN6 —
ADC, input 6. This analog input is always connected to its pin.
P3.30 —
General purpose digital input/output pin.
BLS1 —
LOW-active Byte Lane Select signal (Bank 1).
P3.31 —
General purpose digital input/output pin.
BLS0 —
LOW-active Byte Lane Select signal (Bank 0).
TD1:
CAN1 transmitter output.
External Reset input:
A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor execution to
begin at address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Ground:
0 V reference.
P3.21/A21
44
[5]
P3.22/A22
41
[5]
P3.23/A23/
XCLK
40
[5]
P3.24/CS3
36
[5]
P3.25/CS2
35
[5]
I/O
O
P3.26/CS1
30
[5]
I/O
O
P3.27/WE
29
[5]
I/O
O
I/O
O
I
I/O
O
I
I/O
O
I/O
O
O
I
P3.28/BLS3/
AIN7
28
[2]
P3.29/BLS2/
AIN6
27
[4]
P3.30/BLS1
97
[4]
P3.31/BLS0
96
[4]
TD1
RESET
22
[5]
135
[6]
XTAL1
XTAL2
V
SS
142
[7]
141
[7]
3, 9, 26, 38,
54, 67, 79,
93, 103, 107,
111, 128
139
I
O
I
V
SSA
I
Analog ground:
0 V reference. This should nominally be the same voltage
as V
SS
, but should be isolated to minimize noise and error.
Table 3.
Symbol
Pin description
…continued
Pin
Type
Description
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