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| 型號： | LPC1224FBD48 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | Cortex-M0 with up to 48 kB flash, 4 kB SRAM, RTC, comparator, 10-bit ADC, CRC, DMA and more |
| 中文描述： | Cortex-MO，最大48kB 閃存，4kB靜態(tài)隨機(jī)存儲器，時鐘芯片，比較器，10位ADC,CRC檢測，內(nèi)存直接存取 |
| 封裝： | LPC1224FBD48/101<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;LPC1224FBD48/221<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2 |
| 文件頁數(shù)： | 48/61頁 |
| 文件大?。?/td> | 480K |
| 代理商： | LPC1224FBD48 |
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LPC122X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
48 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
11.5 I
2
C-bus
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[3]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V
IH
(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[4]
C
b
= total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified t
f
.
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[5]
[6]
[7]
The maximum t
HD;DAT
could be 3.45
s and 0.9
s for Standard-mode and Fast-mode but must be less than the maximum of t
VD;DAT
or
t
VD;ACK
by a transition time. This maximum must only be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[8]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[9]
A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system but the requirement t
SU;DAT
= 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
r(max)
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the
Standard-mode I
2
C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
Table 16.
T
amb
=
40
C to +85
C.
[1]
Symbol
f
SCL
Dynamic characteristic: I
2
C-bus pins
Parameter
SCL clock frequency
Conditions
Standard-mode
Fast-mode
Fast-mode Plus
of both SDA and
SCL signals
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Min
0
0
0
-
Max
100
400
1
300
Unit
kHz
kHz
MHz
ns
t
f
fall time
[3][4][5][6]
20 + 0.1
C
b
-
4.7
1.3
0.5
4.0
0.6
0.26
0
0
0
250
100
50
300
120
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
s
s
s
s
s
s
s
s
s
ns
ns
ns
t
LOW
LOW period of the SCL clock
t
HIGH
HIGH period of the SCL clock
t
HD;DAT
data hold time
[2][3][7]
t
SU;DAT
data set-up time
[8][9]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC1224FBD48/101 | 制造商:NXP Semiconductors 功能描述:MCU 32K FLASH CORTEX-M0 48LQFP 制造商:NXP Semiconductors 功能描述:MCU, 32K FLASH, CORTEX-M0, 48LQFP 制造商:NXP Semiconductors 功能描述:MCU, 32K FLASH, CORTEX-M0, 48LQFP; Controller Family/Series:LPC1200; Core Size:32bit; No. of I/O's:39; Supply Voltage Min:3V; Supply Voltage Max:3.6V; Digital IC Case Style:LQFP; No. of Pins:48; Program Memory Size:32KB; RAM Memory ;RoHS Compliant: Yes |
| LPC1224FBD48/101,1 | 功能描述:ARM微控制器 - MCU CORTEX M0 32K FL 4K DMA CRC ADC COMPARTR RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC1224FBD48/101,151 | 制造商:NXP Semiconductors 功能描述:Bulk |
| LPC1224FBD48/1011 | 制造商:NXP Semiconductors 功能描述:LPC1224FBD48/LQFP48/TRAYB//101 |
| LPC1224FBD48/121 | 制造商:NXP Semiconductors 功能描述:MCU 48K FLASH CORTEX-M0 48LQFP 制造商:NXP Semiconductors 功能描述:MCU, 48K FLASH, CORTEX-M0, 48LQFP 制造商:NXP Semiconductors 功能描述:MCU, 48K FLASH, CORTEX-M0, 48LQFP; Controller Family/Series:LPC1200; Core Size:32bit; No. of I/O's:39; Supply Voltage Min:3V; Supply Voltage Max:3.6V; Digital IC Case Style:LQFP; No. of Pins:48; Program Memory Size:48KB; RAM Memory ;RoHS Compliant: Yes |
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