參數(shù)資料
型號(hào): LPC1224FBD48
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: Cortex-M0 with up to 48 kB flash, 4 kB SRAM, RTC, comparator, 10-bit ADC, CRC, DMA and more
中文描述: Cortex-MO,最大48kB 閃存,4kB靜態(tài)隨機(jī)存儲(chǔ)器,時(shí)鐘芯片,比較器,10位ADC,CRC檢測(cè),內(nèi)存直接存取
封裝: LPC1224FBD48/101<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;LPC1224FBD48/221<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2
文件頁數(shù): 16/61頁
文件大?。?/td> 480K
代理商: LPC1224FBD48
LPC122X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
16 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
[1]
After reset, the SWD functions are selected by default on pins PIO0_26 and PIO0_25.
7. Functional description
7.1 ARM Cortex-M0 processor
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption.
7.1.1
System tick timer
The ARM Cortex-M0 includes a System Tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval.
7.2 On-chip flash program memory
The LPC122x contain up to 128 kB of on-chip flash memory.
7.3 On-chip SRAM
The LPC122x contain a total of up to 8 kB on-chip static RAM memory.
7.4 Memory map
The LPC122x incorporates several distinct memory regions, shown in the following
figures.
Figure 4
shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128
peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32
peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows
simplifying the address decoding for each peripheral.
UART1
RXD1
TXD1
SCK
MISO
MOSI
SSEL
SCL
SDA
SWCLK
[1]
SWDIO
[1]
RESET
CLKOUT
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I
O
PIO0_8
PIO0_9
PIO0_14
PIO0_16
PIO0_17
PIO0_15
PIO0_10
PIO0_11
PIO0_18
PIO0_25
PIO0_13
PIO0_12
PIO2_11
PIO2_10
-
-
-
-
-
-
PIO0_26
PIO1_2
-
-
PIO2_12
PIO2_13
-
-
-
-
-
-
-
-
-
-
SSP/SPI
I2C
SWD
Reset
Clockout pin
Table 4.
Peripheral
Pin multiplexing
Function
Type
Available on ports:
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