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參數(shù)資料
| 型號： | LP62S4096E-I |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 512K X 8 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 為512k × 8位低電壓CMOS的SRAM |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 162K |
| 代理商： | LP62S4096E-I |
LP62S4096E-T Series
(January, 2002, Version 2.0)
9
AMIC Technology, Inc.
Write Cycle 2
(6)
(Chip Enable Controlled)
tWC
Address
tAW
tWR3
(4)
tCW1 , tCW2
tAS1
DIN
tDW
tWHZ7
DOUT
tDH
tWP2
WE
CE2
CE1
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1 or high CE2 , and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low WE going high to the end of the
Write cycle.
4. If the CE1 low or CE2 high transition occurs simultaneously with the WE low transition or after the WE
transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE level is high or low.
7. Transition is measured
±500mV from steady state. This parameter is sampled and not 100% tested.
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