參數(shù)資料
型號: LP3936SLX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 顯示驅(qū)動器
英文描述: Lighting Management System for Six White LEDs and One RGB or FLASH LED
中文描述: LED DISPLAY DRIVER, QCC32
封裝: 4.5 X 5.5 MM, 0.80 MM HEIGHT, 0.50 PITCH, CSP-32
文件頁數(shù): 7/20頁
文件大小: 520K
代理商: LP3936SLX
Logic Interface Characteristics
(1.8V
V
DD_IO
V
DD1,2
) (Note 11)
Symbol
Parameter
LOGIC INPUTS DI, SCL, NRST, RGB_EN, CS, MW_SEL
V
IL
Input Low Level
V
IH
Input High Level
I
I
Logic Input Current
f
SCL
Clock Frequency
Conditions
Min
Typ
Max
Units
0.5
V
V
μA
kHz
MHz
V
DD_IO
0.5
1.0
1.0
400
8
I
2
C Mode
MicroWire Mode
LOGIC OUTPUTS DO, CS
V
OL
V
OH
I
L
Output Low Level
Output High Level
Output Leakage Current
I
DO, CS
= 3 mA
I
DO
= 3 mA
V
DO
= 2.8V
0.3
0.6
V
V
μA
V
DD_IO
0.6
V
DD_IO
0.3
1.0
Note 11:
In I
2
C mode operating ratings are limited to 3.0V
V
DD1,2
4.5V and –20C
T
A
+85C.
Control Interface
The LP3936 supports two different interfaces modes:
1) MicroWire/SPI interface
2) I
2
C compatible interface
User can define the interface by MW_SEL pin. The pin
configuration will also change depending on which interface
is selected. The following table shows the selections for both
interface modes.
MW_SEL
1
Interface
MicroWire/SPI
Pin Configuration
Comment
SCL
DI
DO
CS
SCL
CS = SDA
(clock)
(data in)
(data out)
(chip select)
(clock)
(data in/out)
0
I
2
C Compatible
Use pull up resistor for SCL
Use pull up resistor for SDA
MicroWire/SPI Interface
The Microwire transmission consists of 16-bit Write and
Read Cycles. One cycle consists of 7 Address bits, 1 Read/
Write (R/W) bit and 8 Data bits. Read is done in two cycles:
address is provided in the first cycle and the data is sent out
on the next cycle. R/W bit high state defines a Write Cycle
and low defines a Read Cycle. DO output is normally in
high-impedance state and it is active only during Write and
Read Cycles. A pull-up or pull-down resistor may be needed
in DO line if a floating logic signal can cause unintended
current consumption in other circuits where DO is con-
nected.
The Address and Data are transmitted MSB first. The Chip
Select signal CS must be low during the Cycle transmission.
CS resets the interface when high and it has to be taken high
between successive Cycles. Data is clocked in on the rising
edge of the SCLclock signal, while data is clocked out on the
falling edge of SCL.
The MicroWire interface mode can also support SPI inter-
face. The difference with normal SPI interface is that in
LP3936 the Read operation from a new address needs two
read cycles. If repetitive reads are made from the same
address, a correct value is obtained on every read cycle.
MicroWire Write Cycle
20081407
L
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