參數(shù)資料
型號(hào): LP3928
廠商: National Semiconductor Corporation
英文描述: High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator
中文描述: 高速雙向電平轉(zhuǎn)換器和超低壓差CMOS電壓穩(wěn)壓器
文件頁數(shù): 10/11頁
文件大小: 240K
代理商: LP3928
Application Hints
(Continued)
NO-LOAD STABILITY
The LDO of the LP3928 will remain stable and in regulation
with no external load connected to the LDO output V
CCB
.
This is especially important in CMOS RAM keep-alive appli-
cations.
LEVEL SHIFTER DIRECTION CONTROL AND LATCH
CLOCK
The direction of the level shifter is set to Ax
Bx by pulling
the DIRx pin to high. The direction of each of the three
channels can be set individually. In this mode a change at
the LatchClk pin has no effect.
A low at the DIRx pin sets the direction to Bx
Ax. If EN2 is
set to high (enabling latch mode), a rising edge of LatchClk
will update Ax depending on the level at Bx. A falling edge of
LatchClk will not change Ax.
MICRO SMD ASSEMBLY
For assembly recommendations of micro SMD package
please refer to National Semiconductor Application Note
AN-1112.
MICRO SMD LIGHT SENSITIVITY
Exposing the micro SMD device to direct sunlight will cause
misoperation of the device. Light sources such as Halogen
lamps can effect electrical performance if brought near to the
device.
The wavelengths which have most detrimental effect are
reds and infra-reds, which means that the fluorescent light-
ing used inside most buildings has very little effect on per-
formance.
A micro SMD test board was brought to within 1 cm of a
fluorescent desk lamp and the effect on the regulated output
voltage was negligible, showing a deviation of less thanTBD
from nominal.
OPERATION MODES, EN1 AND EN2
The output of the LDO (V
CCB
) is turned off and the level
shifter channels are set to a high Z state by pulling the
enable input pins EN1 and EN2 low.
EN1=0 and EN2=1 turns the LDO on and the level shifter
off.
EN1=1 and EN2=0 turns the LDO on and the latch of the
level shifter is bypassed in B to A direction. The Latch Clock
is not used in this mode. The LatchClk pin should not be left
floating but actively terminated.
EN1=1 and EN2=1 turns the LDO on and activates the latch
in B to A direction.
To assure proper operation, the signal source used to drive
the EN input pins must be able to swing above and below the
specified turn-on/off voltage thresholds listed in the Electrical
Characteristics section under Level Shifter DC Voltage Lev-
els.
Both pins, EN1 and EN2 must be actively terminated.
L
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