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參數(shù)資料
| 型號(hào)： | LMX5001VBC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Dedicated Bluetooth Link Controller |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 198K |
| 代理商： | LMX5001VBC |
Functional Description
(Continued)
CONFIGURATION DATA—Bytes 1 through 9
Bytes 1 through 9 are used to transport LMX3162 Program
Words (PW), via the LMX5001. The LMX3162 is controlled
using 3 Program Words (PW1–PW3), each word being 20
bits long. Detailed information on the content and application
of these Programming Words is provided in the LMX3162
Datasheet.
CONFIGURATION DATA—Bytes 10 and 11
Bytes 10 and 11 contain “transmit bits”. It indicates number
of bits to be transferred when the command in Byte 0 signal
a transmission. This value is 12-bit in length with Byte 10
containing the least significant byte and the lower 4 bits of
Byte 11 containing the remaining 4 most significant bits (ref-
erence Table 1). In the “power down” command, the “trans-
mit bits” field contains wake up point. When the lower 12 bits
of the native clock reaches this point, the Bluetooth unit
comes out of the “power down” mode and wakes up to full
power mode. The LMX5001 and LMX3162 take 3 SYSTICKs
to complete a full power up sequence.
Bit 4 of Byte 11 is used as “l(fā)oadclk”. It is valid only for
“Change to Slave Clock” command. When this bit is set to 1,
the lower 12 bits of the native clock is updated with the value
in the “transmit bits” field. When this bit is 0, the native clock
remains unchanged.
CONFIGURATION DATA—Bytes 12 and 13
Bytes 12 and 13 contain a “Threshold” value. This value is
used by the LMX5001 to test for an acceptable level of cor-
relation between the internal Bluetooth Access Code (refer-
ence Bluetooth Specification) and the Access Code from the
incoming packet. If the resulting maximum correlation ex-
ceeds this “Threshold” value then the LMX5001 achieves a
correlation. The “Correlation” Flag is set in the packet’s pay-
load, and subsequently transferred to the Link Management
Controller (reference
section on LCI Rx Data
).
The Access Code Correlation Threshold is 10 bits in length
with Byte 12 containing the least significant byte of the corre-
lation threshold and the lower 2 bits of Byte 13 containing the
remaining 2 most significant bits (reference Table 1).
Bits 7, 6, and 5 of Byte 13 are used for Receive Attenuation
and Receive/Transmit Polarity (reference Table 1). When Bit
7 is set, the RX/TX switch in Radio Frequency Front End
(RFFE) is set in the TX direction when receiving, which gives
～
20 db attenuation in the receiver to help resolving the inter-
modulation problem. When Bit 6 is set, the polarity of RX
data is inverted. When Bit 5 is set, the polarity of TX data is
inverted.
Bit 4 of Byte 13 is PLLOpenRX. It controls PLL loop when re-
ceiving. The loop is opened if this bit set to 1.
Bit 3 of Byte 13 is RSSI_PH. It controls RSSI value A/D con-
version scheme. If it is set to 1 the conversion uses peak-
hold and the conversion is running throughout the entire re-
ceive phase. If it is set to 0 the conversion is running only
during the correlation phase.
CONFIGURATION DATA—Bytes 14 and 15
Bytes 14 and 15 are assigned to the control of external
modulation components (reference Table 1).
CONFIGURATION DATA—Bytes 16 and 17
Bytes 16 and 17 are assigned GPIO operation (reference
Table 1). Byte 16 is used for GPIO output and Byte 17 is
used for enable and disable. When the corresponding bit in
Byte 17 is set to 0, the GPIO is input, otherwise, it is output.
Bit 3 of Byte 16 has a special meaning. When it is 1, GPIO2
(Bit 4 of Byte 16) outputs a 4 MHz clock. When it is 0, GPIO2
performs regular GPIO function.
CONFIGURATION DATA—Bytes 18 through 25
Bytes 18 through 25 contain the appropriate Sync Word part
of the access code. The Sync Word is a 64-bit value (refer-
ence Table 1).
LMX5001/LMX3162 STATUS DATA TRANSFER
LMX5001 (and LMX3162) status is communicated to the
Link Management Controller by use of the RxData line on
the LCI (supported by RxFrSync and SCLK signals). This
transfer is under the control of the LMX5001, and occurs at
a specific interval (reference Figure 3—LCI Communication
Scheduling).
Note that the Status information which is presented to the
Link Management Controller (via the LCI) details the Status
of the LMX5001 and LMX3162 for the Frame/Slot immedi-
ately prior to the current one - there is a one frame delay in
the transfer of Status information.
The data transfer relative to each Byte is detailed in Table 3
below.
TABLE 3. Status Data Bytes
Byte No.
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
Byte 10
Byte 11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Version Major
GPIO4
Version Minor
0
GPIO5
GPIO3
GPIO2
LSB Maximum Correlation
0
LSB Timescew
0
NC(4)
NC(12)
NC(20)
0
0
GPIO1
GPIO0
0
0
0
0
0
MSB Max Corr.
0
0
0
MSB Timescew
NC(2)
NC(10)
NC(18)
NC(26)
AD value
1
NC(7)
NC(15)
NC(23)
0
0
NC(6)
NC(14)
NC(22)
0
0
NC(5)
NC(13)
NC(21)
0
0
NC(3)
NC(11)
NC(19)
NC(27)
NC(1)
NC(9)
NC(17)
NC(25)
NC(0)
NC(8)
NC(16)
NC(24)
reserved
0
0
0
L
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