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參數(shù)資料
| 型號： | LMX5001VBC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Dedicated Bluetooth Link Controller |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大小： | 198K |
| 代理商： | LMX5001VBC |
Pin Descriptions
(Continued)
Pin
No.
18
Pin Name
I/O
Description
GPIO0
(XTAL Config)
GPIO1
(XTAL Config)
LPXTALI
I/O
XTAL configuration during reset (Note 1).
19
I/O
XTAL configuration during reset (Note 1).
20
I
128 kHz XTAL connection for low power mode. This is used in low power mode. If
the low power mode is not used it is not necessary with at XTAL here. External
128 kHz clock can also be feed in here.
128 kHz XTAL connection.
General Purpose I/O
General Purpose I/O
General Purpose I/O
LCI Data Transmit
LCI Data Receive
LCI Receive Frame Sync.
LCI Transmit Frame Sync.
LCI Serial Clock.
Power Down to Link Management Controller
Power Down Acknowledge from Link Management Controller
PWM signal to make adjustments to the XTAL.
16 MHz XTAL connection. (External clock input).
16 MHz XTAL connection.
Systick generated from the internal LMX5001 Master/Slave Counter.
When low holds the LMX5001 in Idle Mode. A rising edge causes a system load
After a rising edge the LMX5001 will start to load control data from and store
status information to the LMC via the LCI.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LPXTALO
GPIO2
GPIO3
GPIO4
TxData
RxData
RxFrSync
TrFrSync
SCLK
PWDN
PWDNACK
Xtal_adj
XTALI
XTALO
SYSTICK
SYSLOAD
O
I/O
I/O
I/O
I
O
O
O
O
O
I
O
I
O
O
I
37
38
39
V
CC
GND
Reset
Power
Power
I
Reset. After Reset is released the LMX5001 will be in Idle Mode, awaiting a
SYSLOAD.
Should be tied low. This signal is used in production test.
Should be lied low. This signal is used in production test.
Xtal clock output to Link Management Controller. This signal can be disabled
using the Sysload Command (for power saving).
General Purpose I/O
PWM signal to make it possible to adjust the quadrature tank circuit to the
LMX3162.
PWM signal for use in creating an RSSI AD converter.
Output from the external comparator in the RSSI AD converter.
DC Compensation circuit enable. At the beginning of the correlation phase, this
signal is enabled (low) for 15 μs.
Receive data.
40
41
42
Test0
Test1
CLKOUT
I
I
O
43
44
GPIO5
Q_adj
I/O
O
45
46
47
RSSI_adj
COMP_RSSI
S_Field3
O
I
O
48
BT_RxData
I
Note 1:
During Reset GPIO0 and GPIO1 are sampled to setup the Xtal division ratio. The assumed external Xtal frequency is derived using the following relationship:
GPIO1
Low
Low
High
High
GPIO0
Low
High
Low
High
Xtal Division Ratio
Divide by 2 (i.e., 16 MHz XTAL or clock input).
Divide by 3 (i.e., 24 MHz XTAL or clock input).
Divide by 4 (i.e., 32 MHz XTAL or clock input).
Not used.
After Reset is completed, GPIO0 and GPIO1 can be used as normal general purpose I/Os.
L
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