- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385493 > LMX2531LQ1500E (NATIONAL SEMICONDUCTOR CORP) High Performance Frequency Synthesizer System with Integrated VCO PDF資料下載
參數(shù)資料
| 型號： | LMX2531LQ1500E |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | High Performance Frequency Synthesizer System with Integrated VCO |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, LLP-36 |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 561K |
| 代理商： | LMX2531LQ1500E |
1.0 Functional Description
The LMX2531LQ1500E is a low power, high performance
frequency synthesizer system which includes the PLL, VCO,
and partially integrated loop filter. Section 2.0 on program-
ming describes the bits mentioned in this section in more
detail.
1.1 REFERENCE OSCILLATOR INPUT
Because the VCO frequency calibration algorithm is based
on clocks from the OSCin pin, there are certain bits that need
to
be
set
depending
on
XTLSEL ( R6[22:20] ) and XTLDIV ( R7[9:8] ) are both need
to be set based on the OSCin frequency.
the
OSCin
frequency.
1.2 R DIVIDER
The R divider divides the OSCin frequency down to the
phase detector frequency. The only valid R counter values
are 1, 2, 4, 8, 16, and 32. The R divider also has an impact
on the fractional modulus that can be used, if it is greater
than 8.
1.3 N DIVIDER AND FRACTIONAL CIRCUITRY
The N divider on the LMX2531LQ1500E is fractional and can
achieve
any
fractional
denominator
4,194,303. The integer portion of the N counter value, N
Inte-
ger
, is determined by the value of the N word. Because there
is a 16/17/20/21 prescaler, there are restrictions on how
small the N
value can be. This is because this value is
actually formed by several different prescalers in the qua-
druple modulus prescaler in order to achieve the desired
value. The fractional word, N
, is a fraction formed
with the NUM and DEN words. The fractional denominator
value, DEN, can be set from 2 to 4,194,303. The case of
DEN=0 makes no sense, since this would cause an infinite N
value, and the case of 1 makes no sense (but could be
done), because integer mode should be used in these appli-
cations. All other values in this range, like 10, 32,734, or
4,000,000 are all valid. Once the fractional denominator,
DEN, is determined, the fractional numerator, NUM, is in-
tended to be varied from 0 to DEN-1. Sometimes, express-
ing the same fraction, like 1/10, in terms of larger fractions,
like 100/10000, sometimes yields better fractional spurs, but
other times it does not. This can be impacted by the frac-
tional modulator order and the dithering mode selected, as
well as the loop bandwidth, and other application specific
criteria. So in general, the total N counter value is deter-
mined by:
N = N
Integer
+ N
Fractional
In order to calculate the minimum necessary fractional de-
nominator, the R counter value needs to be chosen, so that
the comparison frequency is known. The minimum neces-
sary fractional denominator can be calculated by dividing the
comparison frequency by the greatest common multiple of
the comparison frequency and the OSCin frequency. For
example, consider the case of a 10 MHz crystal and a 200
kHz channel spacing. If the R counter value is chosen to be
2, then the comparison frequency will be 5 MHz. The great-
est common multiple of 200 kHz and 5 MHz is 200 kHz. If
one takes 5 MHz divided by 200 kHz, this is 25. So a
fractional denominator of 25, or any multiple of 25 would
work in this situation. Now consider a second example
where the channel spacing is changed to 30 kHz. If it is again
assumed that the comparison frequency is 5 MHz, then the
greatest common multiple of 30 kHz and 5 MHz is 10 kHz. 5
MHz divided by 10 kHz is 500. In this situation, a fractional
denominator of 500, or any multiple of 500 would suffice. For
between
1
and
a final example, consider an application with a fixed output
frequency of 2110.8 MHz and a crystal frequency of 19.68
MHz. If the R counter is chosen to be 2, then the comparison
frequency is 9.84 MHz. The greatest common multiple of
9.84 MHz and 2110.8 MHz is 240 kHz. 9.84 MHz / 240 kHz
= 41. So the fractional denominator could be 41, or any
multiple of 41. For this last example value, the entire N
counter value would be 214 + 21/41.
The fractional value is achieved with a delta sigma architec-
ture. In this architecture, an integer N counter is modulated
between different values in order to achieve a fractional
value. On this part, the modulator order can be zero (integer
mode), two, three, or four. The higher the fractional modula-
tor order is, the lower the spurs theoretically are. However,
this is not always the case, and the higher order fractional
modulator can sometimes give rise to additional spurious
tones, but this is dependent on the application. This is why it
is an advantage to have the modulator order selectable.
Dithering also has an impact on the fractional spurs, but a
lesser one.
1.4 PHASE DETECTOR
The phase detector compares the outputs of the R and N
counters and puts out a correction current corresponding to
the phase error. The choice of the phase detector frequency
does have an impact on performance. When determining
which phase detector frequency to use, the restrictions on
the R counter values must be taken into consideration.
1.5 PARTIALLY INTEGRATED LOOP FILTER
The LMX2531LQ1500E integrates the third pole (formed by
R3 and C3) and fourth pole (formed by R4 and C4) of the
loop filter. This loop filter can be enabled or bypassed using
the EN_LPFLTR ( R6[15] ). The values for C3, C4, R3, and
R4 can also be programmed independently through the
MICROWIRE interface . Also, the values for R3 and R4 can
be changed during FastLock, for minimum lock time. It is
recommended that the integrated loop filter be set to the
maximum
possible
attenuation
C3=C4=100pF), the internal loop filter is more effective at
reducing certain spurs than the external loop filter. However,
if the attenuation of the internal loop filter is too high, it limits
the maximum attainable loop bandwidth that can be
achieved, which corresponds to the case where the shunt
loop filter capacitor, C1, is zero. Increasing the charge pump
current and/or the comparison frequency increases the
maximum attainable loop bandwidth when designing with the
integrated filter. Furthermore, this often allows the loop filter
to be better optimized and have stronger attenuation. If the
charge pump current and comparison frequency are already
as high as they go, and the maximum attainable loop band-
width is still too low, the resistor and capacitor values can be
decreased or the internal loop filter can even be bypassed.
Note that when the internal loop filter is bypassed, there is
still a small amount of input capacitance on front of the VCO
on the order of 200 pF. For design tools and more informa-
tion on partially integrated loop filters, go to wireless.nation-
al.com.
(R3=R4=40k
,
1.6 LOW NOISE, FULLY INTEGRATED VCO
The LMX2531LQ1500E includes a fully integrated VCO,
including the inductors. In order for optimum phase noise
performance, this VCO has frequency and phase noise cali-
bration algorithms. The frequency calibration algorithm is
necessary because the VCO internally divides up the fre-
quency range into several bands, in order to achieve a lower
L
www.national.com
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMX2531LQ1742 | Evaluation Board Operating Instructions |
| LMX2531LQ1742FPEB | Evaluation Board Operating Instructions |
| LMX3305SLBX | Triple Phase Locked Loop for RF Personal Communications |
| LMX3305 | Triple Phase Locked Loop for RF Personal Communications |
| LMX4168FLQ | Radio Transceiver for DECT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2531LQ1500E/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2531LQ1500E_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High Performance Frequency Synthesizer System with Integrated VCO |
| LMX2531LQ1500EX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High Performance Frequency Synthesizer System with Integrated VCO |
| LMX2531LQ1515E | 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Single 1450MHz to 1580MHz 36-Pin LLP EP T/R 制造商:Texas Instruments 功能描述:CLOCK SYNTHESIZER 1.6GHZ 36LLP |
| LMX2531LQ1515E/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。