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參數(shù)資料
| 型號： | LMX2531LQ1500E |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | High Performance Frequency Synthesizer System with Integrated VCO |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, LLP-36 |
| 文件頁數(shù)： | 16/23頁 |
| 文件大?。?/td> | 561K |
| 代理商： | LMX2531LQ1500E |
2.0 General Programming Information
(Continued)
2.4 REGISTER R3
2.4.1 DEN[21:12] -- Extension for the Fractional Denominator
These are the MSB bits of the DEN word, which have already been discussed.
2.4.2 FoLD[3:0] -- Multiplexed Output for Ftest/LD Pin
The FoLD[3:0] word is used to program the output of the Ftest/LD Pin. This pin can be used for a general purpose I/O pin, a lock
detect pin, and for diagnostic purposes. When programmed to the digital lock detect state, the output of the Ftest/LD pin will be
high when the part is in lock, and low otherwise. Lock is determined by comparing the input phases to the phase detector. The
analog lock detect modes put out a high signal with very fast negative pulses, that correspond to when the charge pump comes
on. This output can be low pass filtered with an RC filter in order to determine the lock detect state. If the open drain state is used,
a pull-up resistor that is much larger than the resistance in the RC filter, to increase the sensitivity of the circuit. For diagnostic
purposes, the options that allow one to view the output of the R counter or the N counter can be very useful. Be aware that the
output voltage level of the Ftest/LD is not equal to the supply voltage of the part, but rather is given by V
OH
and V
OL
in the
electrical characteristics specification.
FoLD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Output Type
High Impedance
Push-Pull
Push-Pull
Push-Pull
N/A
Push-Pull
Open-Drain
Push-Pull
N/A
N/A
N/A
N/A
N/A
N/A
Push-Pull
N/A
Function
Disabled
Logical High State
Logical Low State
Digital Lock Detect
Reserved
N Counter Output Divided by 2
Analog Lock Detect
Analog Lock Detect
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R Counter Output
Reserved
2.4.3 ORDER -- Order of Delta Sigma Modulator
This bit determines the order of the delta sigma modulator in the PLL. In general, higher order fractional modulators tend to
reduce the primary fractional spurs that occur at increments of the channel spacing, but can also create spurs that are at a fraction
of the channel spacing, if there is not sufficient filtering. The optimal choice of modulator order is very application specific,
however, a third order modulator is a good starting point if not sure what to try first.
ORDER
0
Delta Sigma Modulator Order
Fourth
Reset Modulator
(Integer Mode - all fractions are ignored)
Second
Third
1
2
3
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2531LQ1500E/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2531LQ1500E_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High Performance Frequency Synthesizer System with Integrated VCO |
| LMX2531LQ1500EX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High Performance Frequency Synthesizer System with Integrated VCO |
| LMX2531LQ1515E | 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Single 1450MHz to 1580MHz 36-Pin LLP EP T/R 制造商:Texas Instruments 功能描述:CLOCK SYNTHESIZER 1.6GHZ 36LLP |
| LMX2531LQ1515E/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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