參數(shù)資料
型號: LMX2525LQ1321/NOPB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 26 MHz, QCC24
封裝: 5 X 4 MM, 0.75 MM HEIGHT, LLP-24
文件頁數(shù): 5/17頁
文件大小: 237K
代理商: LMX2525LQ1321/NOPB
Programming Description (Continued)
R0 REGISTER
The R0 register address bits (R0 [1:0]) are “00”.
The Rx/Tx bit selects between receive and transmit modes and, in conjunction with the band select bit (BS), the channel spacing
to be synthesized.
The RF_PD bit selects the power down mode of the RF PLL and selected VCO.
The HS bit selects between normal and high speed locking mode.
The BS bit determines which of the two internal VCOs (PDC800 or PDC1500) is active.
The RF N counter consists of the 4-bit programmable counter (RF_B counter), the 3-bit swallow counter (RF_A counter) and the
10-bit delta sigma modulator (RF_FN counter). The equations for calculating the counter values are presented below.
R0 REGISTER
Register
MSB
SHIFT REGISTER BIT LOCATION
LSB
23
22
21
20
19
18
17
16
15
14
13
12
11
10
987654321
0
Data Field
Address
Field
R0
(Default)
RX/
TX
RF_
PD
HS
0
BS
RF_B
[3:0]
RF_A
[2:0]
RF_FN
[9:0]
00
Name
Functions
RX/TX
RX/TX Mode
0=Rx
1= Tx
RF_PD
Power Down of RF Synthesizer
0 = RF synthesizer on (Active mode)
1 = RF synthesizer powered down
HS
Locking Mode
0 = Normal Mode
1 = High Speed Mode
BS
Band Select
1 = RF1 VCO (PDC1500)
0 = RF2 VCO (PDC800)
RF_B [3:0]
RF_B Counter
4-bit programmable counter
0
≤ RF_B ≤ 15 for both bands
RF_A [2:0]
RF_A Counter
3-bit swallow counter
0
≤ RF_A ≤ 7 for PDC1500
0
≤ RF_A ≤ 3 for PDC800
RF_FN [9:0]
RF_FN Counter
10-bit modulus counter
0
≤ RF_FN < FD See Table 6 for FD values.
Counter Name
Symbol
Functions
Modulus Counter
RF_FN
RF N Divider
N=8x RF_B + RF_A + RF_FN/FD (PDC1500)
N=4x RF_B + RF_A + RF_FN/FD (PDC800)
Programmable Counter
RF_B
Swallow Counter
RF_A
LMX2525
www.national.com
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