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參數(shù)資料
| 型號： | LMX2515LQX0701/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 26 MHz, QCC28 |
| 封裝： | 5 X 5 MM, 0.75 MM HEIGHT, LLP-28 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 231K |
| 代理商： | LMX2515LQX0701/NOPB |
Programming Description (Continued)
R1 REGISTER
The R1 register address bits (R1 [1:0]) are “01”.
The SPI_DEF bit allows for the programming of words R3 to R5. Under most circumstances, the SPI_DEF bit should be set to
"1".
The LD bit sets the function of the lock detect pin. Enabling the lock detect function provides a digital lock detect output of the
active RF synthesizer at the LD pin.
The OB_CRL [1:0] bits determine the power level of the RF output buffer. The power level can be adjusted to best meet the
system requirement.
The reference frequency selection bits, OSC_FREQ [1:0], are used to set the reference clock and R divider for use with one of
the following reference frequencies: 12.6 MHz, 14.4 MHz, 25.2 MHz or 26.0 MHz. The LMX2515 uses the OSC_FREQ bits along
with the RF_SEL and RX/TX bits to determine the correct divide ratios needed to meet the required channel spacing for the mode
of operation selected. Refer to Table 6 for a summary of denominator values.
R1 REGISTER
Register
MSB
SHIFT REGISTER BIT LOCATION
LSB
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9876
5
4
3
2
1
0
Data Field
Address
Field
R1
(Default)
SPI_
DEF
001001010000
0
010LDOB_
CRL
[1:0]
OSC_
FREQ
[1:0]
01
Name
Functions
SPI_DEF
Default Register Selection
0 = OFF (Use values set in R0 to R5)
1 = ON (Use default values set in R0 to R2)
LD
Lock Detect
0 = Disable (GND)
1 = Enable
OB_CRL [1:0]
Output Buffer Control
LMX2515LQ1321, LMX2515LQ0701
00 = -10 dBm, -12 dBm
01 = -7 dBm, -8 dBm
10 = -4 dBm, -6 dBm
11 = -2 dBm, -3 dBm
OSC_FREQ [1:0]
Reference Frequency Selection
00 = 12.6 MHz
01 = 14.4 MHz
10 = 25.2 MHz
11 = 26.0 MHz
LMX2515
www.national.com
14
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