參數(shù)資料
型號(hào): LMX2485
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
中文描述: PLL FREQUENCY SYNTHESIZER, 3000 MHz, PQCC24
封裝: 4 X 4 MM, 0.8 MM, PLASTIC, LLP-24
文件頁(yè)數(shù): 21/37頁(yè)
文件大小: 861K
代理商: LMX2485
Functional Description
(Note 9)
(Continued)
CE Pin
Low
RF_PD
X
ATPU
Bit Enabled +
Write to RF
N Counter
X
PLL State
Powered Down
(Asynchronous)
Powered Up
Powered Up
Powered Down
( Asynchronous )
High
High
High
X
0
1
Yes
No
No
1.7 DIGITAL LOCK DETECT OPERATION
The RF PLL digital lock detect circuitry compares the differ-
ence between the phase of the inputs of the phase detector
to a RC generated delay of
e
. To indicate a locked state
(Lock = HIGH) the phase error must be less than the
e
RC
delay for 5 consecutive reference cycles. Once in lock (Lock
= HIGH), the RC delay is changed to approximately
δ
. To
indicate an out of lock state (Lock = LOW), the phase error
must become greater
δ
. The values of
e
and
δ
are dependent
on which PLL is used and are shown in the table below:
PLL
RF
IF
e
δ
10 ns
15 ns
20 ns
30 ns
When the PLL is in the power down mode and the Ftest/LD
pin is programmed for the lock detect function, it is forced
LOW. The accuracy of this circuit degrades at higher com-
parison frequencies. To compensate for this, the DIV4 word
should be set to one if the comparison frequency exceeds 20
MHz. The function of this word is to divide the comparison
frequency presented to the lock detect circuit by 4. Note that
if the MUX[3:0] word is set such as to view lock detect for
both PLLs, an unlocked (LOW) condition is shown whenever
either one of the PLLs is determined to be out of lock.
20087704
L
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21
相關(guān)PDF資料
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LMX2485E 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
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LMX2485ESQX 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
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