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參數(shù)資料
| 型號： | LMX2346TMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum⑩ Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 20/27頁 |
| 文件大小： | 606K |
| 代理商： | LMX2346TMX |
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1.0 Functional Description
(Continued)
1.1 REFERENCE OSCILLATOR
The reference oscillator frequency for the PLL is provided
from an external source via the OSC
in
pin. The reference
buffer circuit supports input frequencies from 5 MHz to 104
MHz with a minimum input sensitivity of 0.4 V
PP
. The refer-
ence buffer circuit has a V
/2 input threshold and can be
driven from an external CMOS or TTL logic gate. The
R_OPT control word is used to optimize the performance of
the reference buffer circuit for best Phase Noise and power
consumption performance based on the frequency of the
reference source. Refer to Section 2.2.5 for details on pro-
gramming the R_OPT control word.
1.2 REFERENCE DIVIDER (R COUNTER)
The reference divider is comprised of a 10-bit CMOS binary
counter that supports a continuous integer divide range from
2 to 1,023. The divide ratio should be chosen such that the
maximum phase comparison frequency of 10 MHz is not
exceeded. The reference divider circuit is clocked by the
output of the reference buffer circuit. The output of the
reference divider circuit feeds the reference input of the
phase detector circuit. The frequency of the reference input
to the phase detector (also referred to as the comparison
frequency) is equal to reference oscillator frequency divided
by the reference divider ratio. Refer to Section 2.2.1 for
details on programming the R Counter.
1.3 RF PRESCALER
The LMX2346/7 contain a fixed 32/33 dual modulus RF
prescaler. The RF Prescaler operates from 100 MHz to 2000
MHz on the LMX2346 and from 100 MHz to 2500 MHz on
the LMX2347.
The complementary F
and F
input pins drive the input of
a bipolar, differential-pair amplifier. The output of the bipolar,
differential-pair amplifier drives a chain of ECL D-type flip-
flops in a dual modulus configuration. The output of the
prescaler is used to clock the subsequent programmable
feedback divider.
1.4 PROGRAMMABLE FEEDBACK DIVIDER
(N COUNTER)
The programmable feedback divider operates in concert with
the RF prescaler to divide the input RF signal (F
) by a
factor of N. The output of the programmable reference di-
vider is provided to the feedback input of the phase detector
circuit. The programmable divider supports a continuous
integer divide range from 992 to 32,767. The divide ratio
should be chosen such that the maximum phase comparison
frequency (F
φ
) of 10 MHz is not exceeded.
The programmable divider circuit is comprised of an A
Counter and a B Counter. The A counter is a 5-bit CMOS
swallow counter programmable from 0 to 31. The B Counter
is a 10-bit CMOS binary counter, programmable from 3 to
1023. Divide ratios less than 992 are achievable as long as
the binary counter value is greater or equal to the swallow
counter value (NB_CNTR
≥
NA_CNTR). Refer to Section
2.3.2 and 2.3.3 for details on programming the NA and NB
Counter. The following equations are useful in determining
and programming a particular value of N:
N = (32 x NB_CNTR) + NA_CNTR
F
IN
= N x F
φ
Definitions
F
φ
Phase Detector Comparison Frequency
F
IN
RF Input Frequency
NA_CNTR
A Counter Value
NA_CNTR
B Counter Value
1.5 PHASE/FREQUENCY DETECTOR
The phase/frequency detector is driven from the N and R
counter outputs. The maximum frequency at the phase de-
tector inputs is 10 MHz. The phase detector outputs control
the charge pump. The polarity of the pump-up or pump-down
control signals are programmed using the PD_POL control
bit, depending on whether the RF VCO tuning characteristics
are positive or negative (see programming description in
Section 2.2.3). The phase/frequency detector has a detec-
tion range of 2
π
to +2
π
.
Phase Comparator And Internal Charge Pump Characteristics
20038411
Note 11:
The minimum width of the pump up and pump down current pulses occur at the CPo pin when the loop is phase-locked.
Note 12:
The diagram assumes that PD_POL = 1
Note 13:
f
R
is the phase comparator input from the R Divider
Note 14:
f
P
is the phase comparator input from the N Divider
Note 15:
CPo is charge pump output
1.6 CHARGE PUMP
The charge pumps directs charge into or out of an external
loop filter. The loop filter converts the charge into a stable
control voltage which is applied to the tuning input of a VCO.
The charge pump steers the VCO control voltage towards V
P
during pump-up events and towards GND during pump-
down events. When locked, CPo is primarily in a Tri-state
condition with small corrections occurring at the phase com-
parison rate.
L
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