參數(shù)資料
型號: LMX2331LMDA
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 2000 MHz, UUC
封裝: DIE
文件頁數(shù): 11/30頁
文件大小: 578K
代理商: LMX2331LMDA
Application Information (Continued)
between 1X and 4X values. This is accomplished by increas-
ing the charge pump output current from 1 mA in the stan-
dard mode to 4 mA in Fastlock.
FASTLOCK CIRCUIT IMPLEMENTATION
A diagram of the Fastlock scheme as implemented in Na-
tional Semiconductors LMX233XL PLL is shown in
Figure 5.
When a new frequency is loaded, and the RF Icp
o bit is set
high the charge pump circuit receives an input to deliver 4
times the normal current per unit phase error while an open
drain NMOS on chip device switches in a second R2 resistor
element to ground. The user calculates the loop filter compo-
nent values for the normal steady state considerations. The
device configuration ensures that as long as a second iden-
tical damping resistor is wired in appropriately, the loop will
lock faster without any additional stability considerations to
account for. Once locked on the correct frequency, the user
can return the PLL to standard low noise operation by send-
ing a MICROWIRE instruction with the RF Icp
o bit set low.
This transition does not affect the charge on the loop filter
capacitors and is enacted synchronous with the charge
pump output. This creates a nearly seamless change be-
tween Fastlock and standard mode.
DS012806-17
FIGURE 4. Open Loop Response Bode Plot
DS012806-18
FIGURE 5. Fastlock PLL Architecture
www.national.com
19
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