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參數(shù)資料
| 型號： | LMX2331LMDA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 10/30頁 |
| 文件大?。?/td> | 578K |
| 代理商： | LMX2331LMDA |
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Application Information
A block diagram of the basic phase locked loop is shown in
Figure 1.
LOOP GAIN EQUATIONS
A linear control system model of the phase feedback for a
PLL in the locked state is shown in
Figure 2. The open loop
gain is the product of the phase comparator gain (K
φ), the
VCO gain (K
VCO/s), and the loop filter gain Z(s) divided by
the gain of the feedback counter modulus (N). The passive
loop filter configuration used is displayed in
Figure 3, while
the complex impedance of the filter is given in
Equation (1).
(1)
The time constants which determine the pole and zero fre-
quencies of the filter transfer function can be defined as
(2)
and
T2 = R2
C2
(3)
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency,
ω, the filter time constants T1 and T2,
and the design constants Kφ,KVCO, and N.
(4)
From
Equations (2), (3) we can see that the phase term will
be dependent on the single pole and zero such that the
phase margin is determined in
Equation (5).
φ(ω) = tan 1 (ω T2) tan1 (ω T1) + 180
(5)
A plot of the magnitude and phase of G(s)H(s) for a stable
loop, is shown in
Figure 4 with a solid trace. The parameter
φ
p shows the amount of phase margin that exists at the point
the gain drops below zero (the cutoff frequency wp of the
loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop band-
width, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison fre-
quency also diminishes, the spurs would have increased by
approximately 6 dB. In the proposed Fastlock scheme, the
higher spur levels and wider loop filter conditions would exist
only during the initial lock-on phase — just long enough to
reap the benefits of locking faster. The objective would be to
open up the loop bandwidth but not introduce any additional
complications or compromises related to our original design
criteria. We would ideally like to momentarily shift the curve
of
Figure 4 over to a different cutoff frequency, illustrated by
the dotted line, without affecting the relative open loop gain
and phase relationships. To maintain the same gain/phase
relationship at twice the original cutoff frequency, other terms
in the gain and phase
Equation (4) and Equation (5) will have
to compensate by the corresponding “1/w” or “1/w
2” factor.
Examination of equations
Equations (2), (3) and Equation (5)
indicates the damping resistor variable R2 could be chosen
to compensate the “w”’ terms for the phase margin. This im-
plies that another resistor of equal value to R2 will need to be
switched in parallel with R2 during the initial lock period. We
must also insure that the magnitude of the open loop gain,
H(s)G(s) is equal to zero at wp’ = 2wp. K
vco,Kφ, N, or the net
product of these terms can be changed by a factor of 4, to
counteract the w
2 term present in the denominator of Equa-
tion (2) and Equation (3). The K
φ term was chosen to com-
plete the transformation because it can readily be switched
DS012806-14
FIGURE 1. Basic Charge Pump Phase Locked Loop
DS012806-15
FIGURE 2. PLL Linear Model
DS012806-16
FIGURE 3. Passive Loop Filter
www.national.com
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