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參數(shù)資料
| 型號(hào)： | LMX2330ATMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 2500 MHz, PDSO20 |
| 封裝： | 0.173 INCH, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 392K |
| 代理商： | LMX2330ATMX |
Application Information (Continued)
FASTLOCK CIRCUIT IMPLEMENTATION
A diagram of the Fastlock scheme as implemented in Na-
tional Semiconductors LMX233xA PLL is shown in
Figure 5.
When a new frequency is loaded, and the RF Icp
o bit is set
high the charge pump circuit receives an input to deliver 4
times the normal current per unit phase error while an open
drain NMOS on chip device switches in a second R2 resistor
element to ground. The user calculates the loop filter compo-
nent values for the normal steady state considerations. The
device configuration ensures that as long as a second iden-
tical damping resistor is wired in appropriately, the loop will
lock faster without any additional stability considerations to
account for. Once locked on the correct frequency, the user
can return the PLL to standard low noise operation by send-
ing a MICROWIRE instruction with the RF Icp
o bit set low.
This transition does not affect the charge on the loop filter
capacitors and is enacted synchronous with the charge
pump output. This creates a nearly seamless change be-
tween Fastlock and standard mode.
DS012331-29
FIGURE 4. Open Loop Response Bode Plot
DS012331-30
FIGURE 5. Fastlock PLL Architecture
www.national.com
16
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| LMX2330L | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2330LEVAL | 功能描述:BOARD EVALUATION LMX2330L RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號(hào) 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
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