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參數(shù)資料
| 型號： | LMX2330ATMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 2500 MHz, PDSO20 |
| 封裝： | 0.173 INCH, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 392K |
| 代理商： | LMX2330ATMX |
Functional Description (Continued)
TABLE 1. Programmable Modes
C1
C2
R16
R17
R18
R19
R20
00
IF Phase
Detector Polarity
IF I
CPo
IF D
o
TRI-STATE
IF LD
IF F
o
01
RF Phase
Detector Polarity
RF I
CPo
RF D
o
TRI-STATE
RF LD
RF F
o
C1
C2
N19
N20
1
0
IF Prescaler
Pwdn IF
1
RF Prescaler
Pwdn RF
TABLE 2. Mode Select Truth Table
Phase Detector Polarity
D
o TRI-STATE
I
CPo
(Note 6)
IF
Prescaler
2330A RF
Prescaler
2331A/32A RF
Prescaler
Pwdn
(Note 7)
0
Negative
Normal
Operation
LOW
8/9
32/33
64/65
Pwrd
Up
1
Positive
TRI-STATE
HIGH
16/17
64/65
128/129
Pwrd
Dn
Note 6: The ICPo LOW current state = 1/4xICPo HIGH current.
Note 7: Activation of the IF PLL or RF PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective fIN inputs
(to a high impedance state). The powerdown function is gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program mode is
loaded, the part will go into powerdown mode when the charge pump reaches a TRI-STATE condition. The R counter functionality does not become disabled until
both IF and RF powerdown bits are activated. The MICROWIRE control register remains active and capable of loading and latching data during all of the powerdown
modes.
TABLE 3. The F
oLD (Pin 10) Output Truth Table
RF R[19]
(RF LD)
IF R[19]
(IF LD)
RF R[20]
(RF F
o)
IF R[20]
(IF F
o)
F
o Output State
0000
Disabled (Note 8)
0100
IF Lock Detect (Note 9)
1000
RF Lock Detect (Note 9)
1100
RF/IF Lock Detect (Note 9)
X
0
1
IF Reference Divider Output
X
0
1
0
RF Reference Divider Output
X
1
0
1
IF Programmable Divider Output
X
1
0
RF Programmable Divider Output
0011
Fastlock (Note 10)
0111
For Internal Use Only
1011
For Internal Use Only
1111
Counter Reset (Note 11)
X = don’t care condition
Note 8: When the FoLD output is disabled, it is actively pulled to a low logic state.
Note 9: Lock detect output provided to indicate when the VCO frequency is in “l(fā)ock.” When the loop is locked and a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked.
Note 10: The Fastlock mode utilizes the FoLD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock
occurs whenever the RF loop’s lcpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock).
Note 11: The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits then N counter resumes counting in “close”
alignment with the R counter. (The maximum error is one prescaler cycle.) If the Reset bits are activated the R counter is also forced to Reset, allowing smooth ac-
quisition upon powering up.
www.national.com
12
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