參數(shù)資料
型號(hào): LMX2330ATMX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類(lèi): PLL合成/DDS/VCOs
英文描述: PHASE LOCKED LOOP, 2500 MHz, PDSO20
封裝: 0.173 INCH, PLASTIC, TSSOP-20
文件頁(yè)數(shù): 2/17頁(yè)
文件大?。?/td> 392K
代理商: LMX2330ATMX
Functional Description
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and the 15- and 18-bit N Counters (in-
termediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first. The
data stored in the shift register is loaded into one of 4 appropriate latches on the rising edge of LE. The last two bits are the Con-
trol Bits. The DATA is transferred into the counters as follows:
Control Bits
DATA Location
C1
C2
0
IF R Counter
0
1
RF R Counter
1
0
IF N Counter
1
RF N Counter
PROGRAMMABLE REFERENCE DIVIDERS (IF AND RF R COUNTERS)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Divide
Ratio
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0000000
00000011
4
0000000
00000100
32767
1111111
11111111
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.
DS012331-1
DS012331-14
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