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參數(shù)資料
| 型號： | LMX1601TM/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16 |
| 封裝： | LEAD FREE, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 631K |
| 代理商： | LMX1601TM/NOPB |
2.0 Programming Description (Continued)
2.3.3
12-BIT Programmable Counter Divide Ratio (Aux B COUNTER)
AUX_B_CNTR
Divide Ratio
11
10
987654321
0
3
00000000001
1
4
00000000010
0
4,095
11111111111
1
Note 10: Divide ratio: 3 to 4,095 (Divide ratios less than 3 are prohibited)
AUX_B_CNTR
≥ AUX_A_CNTR.
See section 2.3.7 for calculation of VCO output frequency.
2.3.4
MAIN_N Register
If the Control Bits (CTL[1:0]) are 1 1 when LE transitions high, data is transferred from the 18-bit shift register into the MAIN_N
register latch which sets 16-bit programmable N divider value. The Main N divider is a 16-bit counter which is fully programmable
from 992 to 65,535 for 2 GHz option and from 240 to 65,535 for 1.1 GHz option. The MAIN_N register consists of the 5-bit (2 GHz
option) or 4-bit (1.1 GHz option) swallow counter (MAIN_A_CNTR) and the 11-bit (2 GHz option) or 12-bit (1.1 GHz option)
programmable counter (MAIN_B_CNTR). Serial data format for the MAIN_N register latch shown below. The divide ratio must be
≥ 992 (2 GHz option) or > 240 (1.1 GHz option) for a continuous divide range. The divide ratio is programmed using the bits
MAIN _A_CNTR and MAIN_B_CNTR as shown in tables 2.3.5 and 2.3.6 The pulse swallow function which determines the divide
ratio is described in Section 2.3.7.
2 GHz option
First Bit
SHIFT REGISTER BIT LOCATION
Last Bit
17
16
15
14
13
12
11
10
987654321
0
MAIN_N
AUX_B_CNTR[10:0]
AUX_A_CNTR[4:0]
1
1.1 GHz option
First Bit
SHIFT REGISTER BIT LOCATION
Last Bit
17
16
15
14
13
12
11
10
987654321
0
MAIN_N
AUX_B_CNTR[11:0]
AUX_A_CNTR[3:0]
1
2.3.5
Swallow Counter Divide Ratio (Main A COUNTER)
2 GHz option (5 bit)
Swallow
MAIN_A_CNTR
Count
(A)
4
3
2
1
0
0
000
0
1
000
0
1
31
111
1
Note 11: Swallow Counter Value: 0 to 31
1.1 GHz option (4 bit)
Swallow
MAIN_A_CNTR
Count
(A)
3
2
1
0
0
000
0
1
000
1
15
111
1
Note 12: Swallow Counter Value: 0 to 15
LMX1600/LMX1601/LMX1602
www.national.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX1601TMX | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LMX1600 2.0 GHz/500 MHz, LMX1601 1.1 GHz/500 MHz, LMX1602 1.1 GHz/1.1 GHz PLLatinuma?￠ Low Cost Dual Frequency Synthesizer |
| LMX1601TMX/NOPB | 功能描述:IC FREQ SYNTHESIZER DUAL 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX1602 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Cost Dual Frequency Synthesizer |
| LMX1602SLB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Cost Dual Frequency Synthesizer |
| LMX1602SLBX | 功能描述:IC FREQ SYNTH DL 1.1GHZ 16-LAMIN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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