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參數(shù)資料
| 型號： | LMX1601TM/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16 |
| 封裝： | LEAD FREE, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 631K |
| 代理商： | LMX1601TM/NOPB |
1.0 Functional Description (Continued)
comparison cycles. The lock detect output is low when the
error between the phase detector outputs is more than 30 ns
for one comparison cycle. The lock detect output is always
low when the PLL is in power down mode. For further
description see Programming Description 2.5.
1.8
POWER CONTROL
Each PLL is individually power controlled by the device EN
pin. The EN
MAIN controls the Main PLL, and the ENAUX
controls the Aux PLL. Activation of EN = LOW (power down)
condition results in the disabling of the respective N and R
counters and de-biasing of their respective fin inputs (to a
high impedance state). The reference oscillator input block
powers down and the OSC
IN pin reverts to a high impedance
state only when both EN pins are LOW. Power down forces
the respective charge pump and phase comparator logic to a
TRI-STATE condition as well as disabling the bandgap ref-
erence block. Power up occurs immediately when the EN pin
is brought high. Power up sequence: Bandgap and Oscillator
blocks come up first, with the remaining PLL functions be-
coming active approx. 1 s later. All programming informa-
tion is retained internally in the chip when in power down
mode. The MICROWIRE control register remains active and
capable of loading and latching in data during power down
mode.
2.0 Programming Description
2.1
MICROWIRE INTERFACE
The descriptions below detail the 18-bit data register loaded through the MICROWIRE Interface. The 18-bit shift register is used
to program the 12-bit Main and Aux R counter registers and the 16-bit Main and Aux N counter registers. The shift register
consists of a 16-bit DATA field and a 2-bit control (CTL [1:0]) field as shown below. The control bits decode the internal register
address. On the rising edge of LE, data stored in the shift register is loaded into one of the 4 appropriate latches (selected by
address bits). Data is shifted in MSB first.
MSB
LSB
DATA [15:0]
CTL [1:0]
18
2 1
0
2.1.1
Register Location Truth Table
When LE transitions high, data is transferred from the 18-bit shift register into one of the 4 appropriate internal latches depending
upon the state of the control (CTL) bits. The control bits decode the internal register address
CTL [1:0]
DATA Location
0
AUX_R Register
0
1
AUX_N Register
1
0
MAIN_R Register
1
MAIN_N Register
2.1.2
Register Content Truth Table
First Bit
SHIFT REGISTER BIT LOCATION
Last Bit
17
16
15
14
13
12
11
10
987654321
0
AUX_R
FoLD
AUX_R_CNTR
0
AUX_N
AUX_B_CNTR
AUX_A_CNTR
0
1
MAIN_R
CP_WORD
MAIN_R_CNTR
1
0
MAIN_N
MAIN_B_CNTR and MAIN_A_CNTR
1
2.2
PROGRAMMABLE REFERENCE DIVIDERS
2.2.1
AUX_R Register
If the Control Bits (CTL [1:0]) are 0 0 when LE transitions high, data is transferred from the 18-bit shift register into a latch which
sets the Aux PLL 12-bit R counter divide ratio. The divide ratio is programmed using the bits AUX_R_CNTR as shown in table
2.2.3. The divider ratio must be
≥ 2. The FoLD word bits controls the multifunction FoLD output as described in section in 2.5.
First Bit
SHIFT REGISTER BIT LOCATION
Last Bit
17
16
15
14
13
12
11
10
987654321
0
AUX_R
FoLD[3:0]
AUX_R_CNTR[11:0]
0
LMX1600/LMX1601/LMX1602
www.national.com
7
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相關代理商/技術參數(shù) |
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|---|---|
| LMX1601TMX | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LMX1600 2.0 GHz/500 MHz, LMX1601 1.1 GHz/500 MHz, LMX1602 1.1 GHz/1.1 GHz PLLatinuma?￠ Low Cost Dual Frequency Synthesizer |
| LMX1601TMX/NOPB | 功能描述:IC FREQ SYNTHESIZER DUAL 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX1602 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Cost Dual Frequency Synthesizer |
| LMX1602SLB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Cost Dual Frequency Synthesizer |
| LMX1602SLBX | 功能描述:IC FREQ SYNTH DL 1.1GHZ 16-LAMIN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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