參數(shù)資料
型號(hào)： LMK04033BISQE/NOPB
廠商： National Semiconductor
文件頁數(shù)： 65/65頁
文件大小： 0K
描述： IC CLOCK CONDITIONER PREC 48LLP
標(biāo)準(zhǔn)包裝： 1
系列： PowerWise®
類型： 時(shí)鐘調(diào)節(jié)器
PLL： 是
輸入： LVCMOS
輸出： LVCMOS，LVDS，2VPECL，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:6
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.16GHz
除法器/乘法器： 是/是
電源電壓： 3.15 V ~ 3.45 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-LLP（7x7）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1275 (CN2011-ZH PDF)
其它名稱： LMK04033BISQEDKR
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V
≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCPout2=VCC/2, PLL2_CP_GAIN
100
= 00b
VCPout2=VCC/2, PLL2_CP_GAIN
400
= 01b
PLL2 Charge Pump Source
ICPoutSOURCE
A
Current (9)
VCPout2=VCC/2, PLL2_CP_GAIN
1600
= 10b
VCPout2=VCC/2, PLL2_CP_GAIN
3200
= 11b
VCPout2=VCC/2, PLL2_CP_GAIN
-100
= 00b
VCPout2=VCC/2, PLL2_CP_GAIN
-400
= 01b
PLL2 Charge Pump Sink
ICPoutSINK
A
Current (9)
VCPout2=VCC/2, PLL2_CP_GAIN
-1600
= 10b
VCPout2=VCC/2, PLL2_CP_GAIN
-3200
= 11b
Charge Pump Sink/Source
ICPout2%MIS
VCPout2=VCC/2, TA = 25 °C
3
10
%
Mismatch
Magnitude of Charge Pump
0.5 V < VCPout2 < VCC - 0.5 V
ICPout2VTUNE
Current vs. Charge Pump
4
%
TA = 25 °C
Voltage Variation
Charge Pump Current vs.
ICPout2%TEMP
4
%
Temperature Variation
ICPout2TRI
Charge Pump Leakage
0.5 V < VCPout2 < VCC - 0.5 V
10
nA
PLL 1/f Noise at 10 kHz offset
PLL2_CP_GAIN = 400 A
-117
PN10kHz
(10). Normalized to
dBc/Hz
PLL2_CP_GAIN = 3200 A
-122
1 GHz Output Frequency
PLL2_CP_GAIN = 400 A
-219
Normalized Phase Noise
PN1Hz
dBc/Hz
Contribution (11)
PLL2_CP_GAIN = 3200 A
-224
Internal VCO Specifications
LMK040x0
1185
1296
LMK040x1
1430
1570
fVCO
VCO Tuning Range
MHz
LMK040x2
1600
1750
LMK040x3
1840
2160
LMK040x0, TA = 25 °C, single-
3
ended
LMK040x1, TA = 25 °C, single-
3
ended
VCO Output power to a
LMK040x2, TA = 25 °C, single-
PVCO
2
dBm
50
Ω load driven by Fout
ended
LMK040x3, TA = 25 °C, single-
0
ended 1840 MHz
LMK040x3, TA = 25 °C, single-
-5
ended 2160 MHz
(9)
This parameter is programmable
(10) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10
kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise,
L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean
crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference
oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of LPLL_flicker(f)
and LPLL_flat(f).
(11) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as:
PN1HZ=LPLL_flat(f)-20log(N)-10log(fCOMP). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz
bandwidth and fCOMP is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
Copyright 2008–2011, Texas Instruments Incorporated
9
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