參數(shù)資料
型號(hào): LMK04031BISQE/NOPB
廠商: National Semiconductor
文件頁(yè)數(shù): 35/65頁(yè)
文件大小: 0K
描述: IC CLOCK CONDITIONER W/PLL 48LLP
標(biāo)準(zhǔn)包裝: 1
系列: PowerWise®
類型: 時(shí)鐘調(diào)節(jié)器
PLL:
輸入: LVCMOS
輸出: LVCMOS,LVDS,2VPECL,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:6
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.57GHz
除法器/乘法器: 是/是
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-LLP(7x7)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 1275 (CN2011-ZH PDF)
其它名稱: LMK04031BISQEDKR
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Register 14
OSCin_FREQ: PLL2 Oscillator Input Frequency Register
The frequency of the PLL2 reference input to the PLL2 Phase Detector (OSCin/OSCin* port) must be
programmed in order to support proper operation of the internal VCO tuning algorithm. This is an 8-bit register
that sets the frequency to the nearest 1-MHz increment.
Table 27. OSCin_FREQ Register Values
OSCin_FREQ [7:0]
VALUE
b7
b6
b5
b4
b3
b2
b1
b0
0
Not Valid
0
1
1 MHz
0
1
0
2 MHz
.
...
1
0
1
0
250 MHz
1
0
1
0
1
Not Valid
.
1
Not Valid
PLL2_R: PLL2_R Counter
The PLL2 R Counter is 12 bits wide. It divides the PLL2 OSCin/OSCin* clock and is connected to the PLL2
Phase Detector.
Table 28. PLL2_R: PLL2_R Counter Values
R [11:0]
VALUE
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
Not Valid
0
1
.
...
1
4095
PLL_MUX: LD Pin Selectable Output
The signal appearing on the LD pin is programmable via the uWire interface and provides access to several
internal signals which may be valuable for either status monitoring during normal operation or for debugging
during the hardware development phase. This pin may be forced to either a HIGH or LOW state, and may also
be configured as specified in Table 29.
40
Copyright 2008–2011, Texas Instruments Incorporated
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