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參數(shù)資料
| 型號： | LMK04031BISQE/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 32/65頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK CONDITIONER W/PLL 48LLP |
| 標準包裝： | 1 |
| 系列： | PowerWise® |
| 類型： | 時鐘調(diào)節(jié)器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS，LVDS，2VPECL，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.57GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-LLP（7x7） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 1275 (CN2011-ZH PDF) |
| 其它名稱： | LMK04031BISQEDKR |
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SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Table 20. EN_PLL2_XTAL: External Crystal Option
EN_PLL2_XTAL
Oscillator Amplifier State
0
OFF
1
ON
EN_Fout: Fout Power Down Bit
The EN_Fout bit allows the Fout port to be enabled or disabled. By default EN_Fout = 0.
CLK Global Enable: Clock Global enable bit
In addition to the external GOE pin, an internal Register 13 bit (b18) can be used to globally enable/disable the
clock outputs via the uWire programming interface. The default value is 1. When CLK Global Enable = 1, the
active output clocks are enabled. The active output clocks are disabled if this bit is 0.
POWERDOWN Bit -- Device Power Down
This bit can power down the entire device. Enabling this bit powers down the entire device and all functional
blocks, regardless of the state of any of the other bits or pins.
Table 21. Power Down Bit Values
POWERDOWN Bit
Mode
0
Normal Operation
1
Entire device powered down
EN_PLL2 REF2X: PLL2 Frequency Doubler control bit
When FOSCin is below 50 MHz, the PLL2 frequency doubler can be enabled by setting EN_PLL2_REF2X = 1. The
default value is 0. When EN_PLL2_REF2X = 1, the signal at the OSCin port bypasses the PLL2_R counter and
is passed through a frequency doubler circuit. The output of this circuit is then input to the PLL2 phase
comparator block. This feature allows the phase comparison frequency to be increased for lower frequency
OSCin sources (< 50 MHz), and can be used with either VXCOs or crystals. For instance, when using a pullable
crystal of 12.288 MHz to drive the OSCin port, the PLL2 phase comparison frequency is 24.576 MHz when
EN_PLL2_REF2X = 1. A higher PLL phase comparison frequency reduces PLL2 in-band phase noise and RMS
jitter. The PLL in-band phase noise can be reduced by approximately 2 to 3 dB. The on-chip loop filter typically is
enabled to reduce PLL2 reference spurs when EN_PLL2_REF2X is enabled. Suggested values in this case are:
R3 = 600
Ω, C3 = 50 pF, R4 = 10 kΩ, C4 = 60 pF.
PLL2 Internal Loop Filter Component Values
Internal loop filter components are available for PLL2, enabling the user to implement either 3rd or 4th order loop
filters without requiring external components. The user may select from a fixed set of values for both the resistors
and capacitors. Internal loop filter resistance values for R3 and R4 can be set individually according to Table 22
and Table 23.
Table 22. PLL2 Internal Loop Filter Resistor Values, PLL2_R3_LF
PLL2_R3_LF [2:0]
RESISTANCE
b2
b1
b0
0
< 600
Ω
0
1
10 k
Ω
0
1
0
20 k
Ω
0
1
30 k
Ω
1
0
40 k
Ω
1
0
1
Invalid
1
0
Invalid
1
Invalid
38
Copyright 2008–2011, Texas Instruments Incorporated
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| LMK04031BISQX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
| LMK04031BISQX/NOPB | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LMK04033BEVAL | 功能描述:時鐘和定時器開發(fā)工具 LMK04033BISQ EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| LMK04033BEVAL/NOPB | 功能描述:時鐘和定時器開發(fā)工具 LMK04033BISQ EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| LMK04033BISQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
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