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參數(shù)資料
| 型號： | LMK04001BISQX/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 26/65頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK CONDITIONER W/PLL 48LLP |
| 標準包裝： | 2,500 |
| 系列： | PowerWise® |
| 類型： | 時鐘調(diào)節(jié)器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS，2VPECL，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:7 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.57GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-LLP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | LMK04001BISQX |
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SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Register R0 To R4
Registers R0 through R4 control the five clock outputs. Register R0 controls CLKout0, Register R1 controls
CLKout1, and so on. Aside from this, the functions of the bits in these registers are identical. The X in
CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the actual clock output which may be
from 0 to 4.
CLKoutX_DIV: Clock Channel Divide Registers
Each of the five clock output channels (0 though 4) has a dedicated 8-bit divider followed by a fixed divide by 2
that is used to generate even integer related versions of the distribution path clock frequency (VCO Divider
output). If the VCO Divider value is even then the Channel Divider may be bypassed (See CLK Output Mux),
giving an effective divisor of 1 while preserving a 50% duty cycle output waveform.
Table 5. CLKoutX_DIV: Clock Channel Divide Values
CLKoutX_DIV [ 7:0 ]
Total Divide Value
b7
b6
b5
b4
b3
b2
b1
b0
0
invalid
0
1
2
0
1
0
4
0
1
6
0
1
0
8
0
1
0
1
10
-
--
-
1
510
EN_CLKoutX: Clock Channel Output Enable
Each Clock Output Channel may be either enabled or disabled via the Clock Output Enable control bits. Each
output enable control bit is gated with the Global Output Enable input pin (GOE) and Global Output Enable bit
(EN_CLKout_Global). The GOE pin provides an internal pull-up so that if it is unterminated externally, the clock
output states are determined by the Clock Output Enable Register bits. All clock outputs can be set to the low
state simultaneously if the GOE pin is pulled low by an external signal. If EN_CLKout_Global is programmed to 0
all outputs are turned off. If both GOE and EN_CLKout_Global are low the clock outputs are turned off.
Table 6. EN_CLKoutX: Clock Channel Output Enable Control Bits
BIT NAME
BIT = 1
BIT = 0
DEFAULT
EN_CLKout0
ON
OFF
EN_CLKout1
ON
OFF
EN_CLKout2
ON
OFF
ON
EN_CLKout3
ON
OFF
EN_CLKout4
ON
OFF
EN_CLKout_Global
According to individual channel
All EN_CLKout X = OFF
-
settings
Note the default state of CLKout2 is ON after power on or RESET assertion. The nominal frequency is 62 MHz
(LMK040x1) or 81 MHz (LMK040x3). This is based on a channel divide value of 12 and default VCO_DIV value
of 2. If an active CLKout2 at power on is inappropriate for the user’s application, the following method can be
employed to shut off CLKout2 during system initialization:
When the device is powered on, holding the GOE pin LOW will disable all clock outputs. The device can be
programmed while the GOE is held LOW. The state of CLKout2 can be altered during device programming
according to the user’s specific application needs. After device configuration is complete, the GOE pin should
be set HIGH to enable the active clock channels.
32
Copyright 2008–2011, Texas Instruments Incorporated
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