參數(shù)資料
型號： LMK04001BISQX/NOPB
廠商： National Semiconductor
文件頁數(shù)： 2/65頁
文件大?。?/td> 0K
描述： IC CLOCK CONDITIONER W/PLL 48LLP
標準包裝： 2,500
系列： PowerWise®
類型： 時鐘調(diào)節(jié)器
PLL： 是
輸入： LVCMOS
輸出： LVCMOS，2VPECL，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:7
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.57GHz
除法器/乘法器： 是/是
電源電壓： 3.15 V ~ 3.45 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-LLP（7x7）
包裝： 帶卷 (TR)
其它名稱： LMK04001BISQX
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V
≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Fine Tuning Sensitivity
LMK040x0
7 to 9
(The range displayed in the
LMK040x1
8 to 11
typical column indicates the
LMK040x2
9 to 14
lower sensitivity is typical at
KVCO
the lower end of the tuning
MHz/V
range, and the higher tuning
sensitivity is typical at the
LMK040x3
14 to 26
higher end of the tuning
range).
After programming R15 for
Allowable Temperature Drift
lock, no changes to output
|
ΔTCL|
for Continuous Lock
125
°C
configuration are permitted to
(12)
guarantee continuous lock
Internal VCO Open Loop Phase Noise and Jitter
Offset = 1 kHz
-66
Offset = 10 kHz
-94
LMK040x0
fVCO = 1185 MHz
Offset = 100 kHz
-119
SSB Phase Noise
dBc/Hz
Offset = 1 MHz
-139
PLL2 = Open Loop
Measured at Fout
Offset = 10 MHz
-158
Offset = 20 MHz
-163
Offset = 1 kHz
-64
Offset = 10 kHz
-91
LMK040x0
fVCO = 1296 MHz
Offset = 100 kHz
-117
SSB Phase Noise
dBc/Hz
Offset = 1 MHz
-138
PLL2 = Open Loop
Measured at Fout
Offset = 10 MHz
-157
Offset = 20 MHz
-161
L(f)Fout
Offset = 1 kHz
-61
Offset = 10 kHz
-91
LMK040x1
fVCO = 1440 MHz
Offset = 100 kHz
-117
SSB Phase Noise
dBc/Hz
Offset = 1 MHz
-138
PLL2 = Open Loop
Measured at Fout
Offset = 10 MHz
-158
Offset = 20 MHz
-160
Offset = 1 kHz
-58
Offset = 10 kHz
-89
LMK040x1
fVCO = 1560 MHz
Offset = 100 kHz
-115
SSB Phase Noise
dBc/Hz
Offset = 1 MHz
-137
PLL2 = Open Loop
Measured at Fout
Offset = 10 MHz
-157
Offset = 20 MHz
-162
(12) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was
at the time that the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register,
even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if
the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R0 register to
ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the
frequency range of -40 °C to 85 °C without violating specifications.
10
Copyright 2008–2011, Texas Instruments Incorporated
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