參數(shù)資料
型號: LM5046MHX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, 540 kHz SWITCHING FREQ-MAX, PDSO28
封裝: TSSOP-28
文件頁數(shù): 20/32頁
文件大小: 888K
代理商: LM5046MHX
HICCUP MODE CURRENT LIMIT RESTART
The operation of the hiccup mode restart circuit is explained
in the Functional Description section. During a continuous
current limit condition, the RES pin is charged with 30A cur-
rent source. The restart delay time required to reach the 1.0V
threshold is given by:
This establishes the number of current limit events allowed
before the IC initiates a hiccup restart sequence. For exam-
ple, if the C
RES=0.01F, the time TCS as noted in Figure 22
below is 334s. Once the RES pin reaches 1.0V, the 30A
current source is turned-off and a 10A current source is
turned-on during the ramp up to 4V and a 5A is turned on
during the ramp down to 2V. The hiccup mode off-time is giv-
en by:
With a C
RES=0.01F, the hiccup time is 49ms. Once the hic-
cup time is finished, the RES pin is pulled-low and the SS pin
is released allowing a soft-start sequence to commence.
Once the SS pin reaches 1V, the PWM pulses will commence.
The hiccup mode provides a cool-down period for the power
converter in the event of a sustained overload condition there-
by lowering the average input current and temperature of the
power components during such an event.
30147816
FIGURE 22. Hiccup Mode Delay and Soft-Start Timing Diagram
Augmenting the Gate Drive Strength
The LM5046 includes powerful 2A integrated gate drivers.
However, in certain high power applications (>500W), it might
be necessary to augment the strength of the internal gate
driver to achieve higher efficiency and better thermal perfor-
mance. In high power applications, typically, the I2xR loss in
the primary MOSFETs is significantly higher than the switch-
ing loss. In order to minimize the I2xR loss, either the primary
MOSFETs are paralleled or MOSFETs with low R
DS (on) are
employed. Both these scenarios increase the total gate
charge to be driven by the controller IC. An increase in the
gate charge increases the FET transition time and hence in-
creases the switching losses. Therefore, to keep the total
losses within a manageable limit the transition time needs to
be reduced.
Generally, during the miller capacitance charge/discharge the
total available driver current is lower during the turn-off pro-
cess than during the turn-on process and often it is enough to
speed-up the turn-off time to achieve the efficiency and ther-
mal goals. This can be achieved simply by employing a PNP
device, as shown in Figure 23, from gate to source of the
power FET. During the turn-on process, when the LO1 goes
high, the current is sourced through the diode D1 and the BJT
Q1 provides the path for the turn-off current. Q1 should be
located as close to the power FET as possible so that the turn-
off current has the shortest possible path to the ground and
does not have to pass through the controller.
27
www.national.com
LM5046
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