
Table 1: Soft-Stop in Fault
Conditions
Fault Condition
SSSR
UVLO
(UVLO<1.25V)
Soft-Stop
3x the charging rate
OVP
(OVP>1.25V)
Hard-Stop
Hiccup
(CS>0.75 and RES>1V)
Soft-Stop
6x the charging rate
VCC/VREF UV
Hard-Stop
Internal Thermal Limit
Hard-Stop
Note: All the above conditions are valid with SSOFF pin tied
to GND. If SSOFF=5V, the LM5046 hard-stops in all the con-
ditions. The SS pin remains high in all the conditions until the
SSSR pin reaches 1V.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the
integrated circuit in the event the maximum rated junction
temperature is exceeded. When activated, typically at 160°C,
the controller is forced into a shutdown state with the output
drivers, the bias regulators (VCC and REF) disabled. This
helps to prevent catastrophic failures from accidental device
overheating. During thermal shutdown, the SS and SSSR ca-
pacitors are fully discharged and the controller follows a nor-
mal start-up sequence after the junction temperature falls to
the operating level (140 °C).
Applications Information
30147862
FIGURE 9. Operating States of the PSFB Topology
PHASE-SHIFTED FULL-BRIDGE OPERATION
The phase shifted full-bridge topology is a derivative of the
conventional full-bridge topology. When tuned appropriately
the PSFB topology achieves zero voltage switching (ZVS) of
the primary FETs while maintaining constant switching fre-
quency. The ZVS feature is highly desirable as it reduces both
the switching losses and the EMI emissions. The realization
of the PSFB topology using the LM5046 is explained as fol-
lows:
Operating State 1 (Power Transfer/Active Mode)
The power transfer mode of the PSFB topology is similar to
the hard switching full-bridge i.e. When the FETs in the diag-
onal of the bridge are turned-on (HO1 & LO2 or HO2 & LO1),
a power transfer cycle from the primary to the secondary is
initiated.
Figure 9 depicts the case where the diagonal switch-
es HO1 and LO2 are activated. In this state, full VIN is applied
to the primary of the power transformer, which is typically
stepped down on the secondary winding.
Operating State 2 (Active to Passive Transition)
At the end of the power transfer cycle, PWM turns off switch
LO2. In the primary side, the reflected load current plus the
magnetizing current propels the SW2 node towards VIN. The
active to passive transition is finished when either the body
diode of HO2 is forward-biased or HO2 is turned-on, whichev-
er happens earlier. A delay can be introduced by setting RD2
to an appropriate value, such that HO2 is turned-on only after
the body-diode is forward biased. In this mode, the I
mag
+I
Lpeak act as a current source charging the parasitic capacitor
located at the node SW2. At light load conditions, it takes a
longer time to propel SW node towards VIN.
The active to passive transition time can be approximated by
using the following formula:
19
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LM5046