參數(shù)資料
型號： LM1229YA
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 運動控制電子
英文描述： I2C Compatible CMOS TV RGB and Deflection Processor
中文描述： WAVEFORM GENERATION, PQFP64
封裝： PLASTIC, QFP-64
文件頁數(shù)： 21/27頁
文件大?。?/td> 969K
代理商： LM1229YA
Application Register Detail
(Continued)
GREEN Gain Control
Register
GREEN GAIN
Addr
0x01
Bit 7
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GGAIN[6:0]
Bits 6–0: Sets the gain level of the green video channel. A value of 0x7F generates the maximum green gain. A value of 0x00
generates the minimum green gain.
BLUE Gain Control
Register
BLUE GAIN
Addr
0x02
Bit 7
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BGAIN[6:0]
Bits 6–0: Sets the gain level of the blue video channel. A value of 0x7F generates the maximum blue gain. A value of 0x00
generates the minimum blue gain.
CONTRAST Control
Register
CONTRAST
Addr
0x03
Bit 7
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONTRAST[6:0]
Bits 6–0: Sets the contrast level three video channels. A value of 0x7F generates the maximum contrast. A value of 0x00
generates the minimum contrast.
DAC 1 Control
Register
DAC 1
Addr
0x04
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DAC1[7:0]
Bits 7–0: Sets the DAC 1 DC output level at pin 39. A full scale value of 0xFF generates the maximum DC output level. A value
of 0x00 generates the minimum DC level.
DAC 2 Control
Register
DAC 2
Addr
0x05
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DAC2[7:0]
Bits 7–0: Sets the DAC 2 DC output level at pin 38. A full scale value of 0xFF generates the maximum DC output level. A value
of 0x00 generates the minimum level.
DAC 3 Control
Register
DAC 3
Addr
0x06
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DAC3[7:0]
Bits 7–0: Sets the DAC 3 DC output level at pin 37. A full scale value of 0xFF generates the maximum DC output level. A value
of 0x00 generates the minimum level.
BRIGHTNESS Control
Register
BRIGHTNESS
Addr
0x07
Bit 7
Bit 6
Bit 5
Bit 4
BRIGHTNESS[7:0]
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7–0: Sets the brightness level of the RGB outputs. A full scale value of 0xFF generates the minimum DC video black level
(darkest). A value of 0x00 generates the maximum DC black level (brightest).
OFFSET Control
Register
OFFSET
Addr
0x08
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
Bit 2
DC_Offset[3:0]
Bit 1
Bit 0
Bits 3–0: Determines the video reference level at the RGB video outputs on pins 57, 58 and 59. A setting of 0xF gives a DC
Offset of about 0.5V and 0x0 gives a DC Offset of about 1.4V.
GLOBAL
Register
GLOBAL
Addr
0x09
Bit 7
INCR
Bit 6
X
Bit 5
DCF
Bit 4
VB
Bit 3
CLAMP
Bit 2
HB
Bit 1
PSAVE
Bit 0
BLANK
Bit 7: When set to 0, the I
2
C auto increment function is active. When set to a 1, the I
2
C auto increment function is disabled. In
the auto increment mode, a given register can be updated continuously using an ADDR - DATA - DATA - ... - DATA
transmission sequence.
Bit 5: When set to 0, the outputs of DACs 1–3 are full scale (0V–4.2V). When this bit is a 1, the output DC range is halved
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