
A
0
- A
10
D
OUT
t
WC
t
AW
t
CW
t
WP
t
WHZ
t
OW
t
DH
t
DW
t
WR
(NOTE 3)
t
AS
(NOTE 2)
(NOTE 4)
5116S-4
WE
CE
D
IN
(NOTE 5)
(NOTE 6)
1. WE must be HIGH when there is a change in A
- A
.
2. When CE and WE are both LOW at the same time, write occurs during the period t
.
3. t
is the time from the rise of CE or WE, whichever is first, to the end of the write cycle.
4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance.
5. D
outputs data with the same logic level as the input data of this write cycle.
6. If CE is LOW during this period, the input/output pins are in the output state. During this state, input
signals of opposite logic level must not be applied.
OE = 'LOW'
NOTES:
Figure 5. Write Cycle 1 (Note 1)
A
0
- A
10
D
OUT
t
WC
t
AW
(NOTE 2)
WE
D
IN
t
CW
t
WP
t
OHZ
t
OW
t
WR
t
DH
t
DW
(NOTE 3)
t
AS
t
OLZ
OE
CE
(NOTE 5)
(NOTE 6)
(NOTE 4)
5116S-5
1. WE must be HIGH when there is a change in A
- A
.
2. When CE and WE are both LOW at the same time, write occurs during the period t
.
3. t
is the time from the rise of CE or WE, whichever is first, to the end of the write cycle.
4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance.
5. D
outputs data with the same logic level as the input data of this write cycle.
6. If CE and OE are LOW during this period, the input/output pins are in the output state. During this state, input
signals of opposite logic level must not be applied.
NOTES:
Figure 6. Write Cycle 2 (Note 1)
LH5116S
CMOS 16K (2K
×
8) Static RAM
6