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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� LFX200EB-03FN256I
寤犲晢锛� Lattice Semiconductor Corporation
鏂囦欢闋佹暩(sh霉)锛� 67/119闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 210KGATES 256FPBGA
妯欐簴鍖呰锛� 90
绯诲垪锛� ispXPGA®
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 2704
RAM 浣嶇附瑷堬細 113664
杓稿叆/杓稿嚭鏁�(sh霉)锛� 160
闁€鏁�(sh霉)锛� 210000
闆绘簮闆诲锛� 2.3 V ~ 3.6 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 105°C
灏佽/澶栨锛� 256-BGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�鐣跺墠绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�
Lattice Semiconductor
ispXPGA Family Data Sheet
47
ispXPGA 1200B/C & ispXPGA 1200EB/EC PIC Timing Parameters
Reset/Set
tLASSRO
Asynchronous Set/Reset to Output
鈥�
1.09
鈥�
1.17
鈥�
1.35
ns
tLASSRPW
Asynchronous Set/Reset Pulse Width
4.19
鈥�
4.50
鈥�
5.18
鈥�
ns
tLASSRR
Asynchronous Set/Reset Recovery
鈥�
0.51
鈥�
0.55
鈥�
0.63
ns
tLSSR_S
Synchronous Set/Reset Setup Time
-0.03
鈥�
-0.03
鈥�
-0.03
鈥�
ns
tLSSR_H
Synchronous Set/Reset Hold Time
0.03
鈥�
0.03
鈥�
0.03
鈥�
ns
1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices.
Timing v.2.1
2. tLCTHRUL quoted bit by bit.
Parameter
Description
-5
1
-4
-3
Units
Min.
Max.
Min.
Max.
Min.
Max.
Register/Latch Delays
tIO_CO
Register Clock to Output Delay
鈥�
1.01
鈥�
1.09
鈥�
1.25
ns
tIO_S
Register Setup Time (Data before Clock)
0.05
鈥�
0.05
鈥�
0.06
鈥�
ns
tIO_H
Register Hold Time (Data after Clock)
0.06
鈥�
0.06
鈥�
0.07
鈥�
ns
tIOCE_S
Register Clock Enable Setup Time
-0.03
鈥�
-0.03
鈥�
-0.03
鈥�
ns
tIOCE_H
Register Clock Enable Hold Time
0.13
鈥�
0.15
鈥�
ns
tIO_GO
Latch Gate to Output Delay
鈥�
0.85
鈥�
0.91
鈥�
1.05
ns
tIOL_S
Latch Setup Time
0.05
鈥�
0.05
鈥�
0.06
鈥�
ns
tIOL_H
Latch Hold Time
0.06
鈥�
0.06
鈥�
0.07
鈥�
ns
tIOLPD
Latch Propagation Delay (Transparent Mode)
鈥�
0.09
鈥�
0.10
鈥�
0.12
ns
tIOASRO
Asynchronous Set/Reset to Output
鈥�
1.17
鈥�
1.26
鈥�
1.45
ns
tIOASRPW
Asynchronous Set/Reset Pulse Width
4.19
鈥�
4.50
鈥�
5.18
鈥�
ns
tIOASRR
Asynchronous Set/Reset Recovery Time
鈥�
0.23
鈥�
0.25
鈥�
0.29
ns
Input/Output Delays
tIOBUF
Output Buffer Delay
鈥�
0.99
鈥�
1.06
鈥�
1.22
ns
tIOIN
Input Buffer Delay
鈥�
0.71
鈥�
0.76
鈥�
0.87
ns
tIOEN
Output Enable Delay
鈥�
0.52
鈥�
0.56
鈥�
0.64
ns
tIODIS
Output Disable Delay
鈥�
-0.11
鈥�
-0.10
鈥�
-0.09
ns
tIOFT
Feed-thru Delay
鈥�
0.19
鈥�
0.20
鈥�
0.23
ns
1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices.
Timing v.2.1
ispXPGA 1200B/C & ispXPGA 1200EB/EC PFU Timing Parameters (Cont.)
Over Recommended Operating Conditions
Parameter
Description
-5
1
-4
-3
Units
Min.
Max.
Min.
Max.
Min.
Max.
SELECT
DEVICES
DISCONTINUED
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鍙冩暩(sh霉)鎻忚堪
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LFX200EB-03FN516I 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 E-Ser210K Gt ispJTA G 2.5/3.3V -3 Spd I RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
LFX200EB-04F256C 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 210K Gates, 160 I/O 2.5/3.3V, -4 speed RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
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