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參數(shù)資料
| 型號： | LC89058W-E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁數(shù)： | 16/46頁 |
| 文件大小： | 284K |
| 代理商： | LC89058W-E |
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LC89058W-E
No.A1056-23/64
10.1.7 Output clocks (RMCK, RBCK, RLRCK, SBCK, SLRCK)
The LC89058W-E features two clock systems (R and S systems) in order to supply the various needed clocks to
peripheral devices such as A/D converter and DSP.
The clock output settings for the R and S systems are done with PLLACC, PLLDV1, PLLVD2, PRSEL[1:0],
XRSEL[1:0], XRBCK[1:0], XRLRCK[1:0], PSBCK[1:0], PSLRCK[1:0], XSBCK[1:0], and XSLRCK[1:0].
Setting range for each clock output pin when the PLL is used as source
(1) RMCK: Selection from 1/1, 1/2, and 1/4 of PLLACC, PLLDV0, PLLDV1, or 512fs
(2) RBCK: 64fs output
(3) RLRCK: fs output
(4) SBCK: Selection from 128fs, 64fs, 32fs, and 16fs
(5)SLRCK: Selection from 2fs, fs, 1/2fs, and 1/4fs
Setting range for each clock output pins when the XIN is used as source
(1) RMCK: Selection from 1/1, 1/2, and 1/4 of 12.288MHz or 24.576MHz
(2) RBCK: Selection from 12.288MHz, 6.144MHz, and 3.072MHz
(3) SBCK: Selection from 12.288MHz, 6.144MHz, and 3.072MHz
(4) RLRCK: Selection from 192kHz, 96kHz, and 48kHz
(5) SLRCK: Selection from 192kHz, 96kHz, and 48kHz
The polarity of RMCK can be reversed with RMCKP.
The polarity of RBCK, RLRCK, SBCK, and SLRCK can be reversed with RBCKP, RLRCKP, SBCKP, and SLRCKP.
Table 10.3 List of Output Clock Frequencies (Bold Items = Initial Settings)
PLL Source (Internal VCO CK)
XIN Source (XIN input CK)
Output Pin Name
512fs
12.288MHz
24.576MHz
RMCK
512fs
256fs
128fs
12.288MHz
6.144MHz
24.576MHz
12.288MHz
6.144MHz
RBCK
64fs
12.288MHz
6.144MHz
3.072MHz
(RMCK=24.576MHz)
(RMCK
≥12.288MHz)
(RMCK
≥6.144MHz)
RLRCK
fs
192kHz
96kHz
48kHz
SBCK
128fs
64fs
32fs
16fs
12.288MHz
6.144MHz
3.072MHz
(RMCK=24.576MHz)
(RMCK
≥12.288MHz)
(RMCK
≥6.144MHz)
SLRCK
2fs
fs
fs/2
fs/4
192kHz
96kHz
48kHz
Notes:
RBCK and SBCK output clock must not quicken more than RMCK output clock frequency. Also, RBCK and SBCK
output clock are set to become 1/2 or less of RMCK output clock at XIN source. If it doesn’t follow these conditions,
RBCK and SBCK clocks are not output.
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