No. 5663-7/16
LC83026E
Parameter
Symbol
Conditions
Ratings
Unit Notes
min
typ
max
[External DRAM Access Timing]
RAS high-level pulse width
tRP
80
ns
7
RAS low-level pulse width
tRAS
700
ns
7
CAS high-level pulse width
tCP
50
ns
7
CAS low-level pulse width
tCAS
95
ns
7
CAS cycle time
tPC
175
ns
7
RAS to CAS delay time
tRCD
60
ns
7
CAS hold time
tCSH
170
ns
7
RAS hold time
tRSH
95
ns
7
RAS address setup time
tASR
60
ns
7
RAS address hold time
tRAH
20
ns
7
CAS address setup time
tASC
30
ns
7
CAS address hold time
tCAH
90
ns
7
DWRT pulse width
tWP
95
ns
7
Write command setup time
tWCS
12
ns
7
Write command hold time
tWCH
65
ns
7
Output data setup time
tDSO
30
ns
7
Output data hold time
tDHO
100
ns
7
C1
13
pF
8
Crystal oscillator
C2
29
pF
8
L
1.5
H
8
Current drain
IDD
60
95
mA
9
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
Unit Notes
min
typ
max
[A/D Converter Block]
Total harmonic distortion
A-THD
1 kHz, at 0 dB
0.05
%
10
Signal-to-noise ratio
A-S/N
1 kHz, at 0 dB
75
80
dB
10,11
Crosstalk
A-C T
1 kHz, at 0 dB
–75
dB
10,11
[D/A Converter Block]
Total harmonic distortion
D-THD
1 kHz, at 0 dB
0.01
%
10
Signal-to-noise ratio
D-S/N
1 kHz, at 0 dB
85
dB
10,11
Crosstalk
D-C T
1 kHz, at 0 dB
–80
dB
10,11
Electrical Characteristics 2 at Ta = 25°C, all VDD = 5.0 V, all VSS = 0 V unless otherwise specified
Notes:
1. TTL output level pins: ASO, FS384O, BCKO, LRCKO, D0 to D7, A0 to A8, RAS, CAS, DREAD, DWRT
2. CMOS intermediate current output pins: P3, P4, SIAK
3. N-channel open drain intermediate current output pins: P0 to P2
4. Low Schmitt input pins: BCKI, ASI, LRCKI, D0 to D7, FS384I
5. Normal input pins: P0 to P2, TEST1 to TEST5, SELC, SAIF, SAOF
6. Schmitt input pins: RES, SI, SICK, SIRQ, SRDY, OSC1
7. When the load capacitance is 50 pF.
8. The values for the oscillator capacitors C1 and C2 include the line capacitances.
9. The typical values for the current drain are for VDD = 5 V, room temperature, and typical samples.
10. Fs = 44.1 kHz and 20 kHz low-pass filter used. Measurement is with the external circuit structure and constants in the Sanyo evaluation board.
11. With the weight A filter used.
Output timing to the external DRAM.
See Figure 8.
Output timing to the external DRAM.
See Figure 8.
OSC1 and OSC2. See Figure 2.
For VDD1, VDD2, and VDD3 when
operating at 33.8688 MHz.